CORDIC Research Articles

Privacy-Preserving Object Detection for Medical Images With Faster R-CNN

In this paper, we propose a lightweight privacy-preserving Faster R-CNN framework (SecRCNN) for object detection in medical images. Faster R-CNN is one of the most outstanding deep learning models for object detection. Using SecRCNN, healthcare centers can efficiently complete privacy-preserving computations of Faster R-CNN via the additive secret sharing technique and edge computing. To implement SecRCNN, we design a series of interactive protocols to perform the three stages of Faster R-CNN, namely feature map extraction, region proposal and regression and classification. To improve the efficiency of SecRCNN, we improve the existing secure computation sub-protocols involved in SecRCNN, including division, exponentiation and logarithm. The newly proposed sub-protocols can dramatically reduce the number of messages exchanged during the iterative approximation process based on the coordinate rotation digital computer algorithm. Moreover, the effectiveness, efficiency and security of SecRCNN are demonstrated through comprehensive theoretical analysis and extensive experiments. The experimental findings show that the communication overhead in computing division, logarithm and exponentiation decreases to 36.19%, 73.82% and 43.37%, respectively.

Low-Latency and Minor-Error Architecture for Parallel Computing XY-like Functions with High-Precision Floating-Point Inputs

This paper proposes a novel architecture for the computation of XY-like functions based on the QH CORDIC (Quadruple-Step-Ahead Hyperbolic Coordinate Rotation Digital Computer) methodology. The proposed architecture converts direct computing of function XY to logarithm, multiplication, and exponent operations. The QH CORDIC methodology is a parallel variant of the traditional CORDIC algorithm. Traditional CORDIC suffers from long latency and large area, while the QH CORDIC has much lower latency. The computation of functions lnx and ex is accomplished with the QH CORDIC. To solve the problem of the limited range of convergence of the QH CORDIC, this paper employs two specific techniques to enlarge the range of convergence for functions lnx and ex, making it possible to deal with high-precision floating-point inputs. Hardware modeling of function XY using the QH CORDIC is plotted in this paper. Under the TSMC 65 nm standard cell library, this paper designs and synthesizes a reference circuit. The ASIC implementation results show that the proposed architecture has 30 more orders of magnitude of maximum relative error and average relative error than the state-of-the-art. On top of that, the proposed architecture is also superior to the state-of-the-art in terms of latency, word length and energy efficiency (power × latency × period /efficient bits).

Deep image compression with lifting scheme: Wavelet transform domain based on high‐frequency subband prediction

Image compression is the most important image processing method extensively deployed in different appliances. “Discrete wavelet transform (DWT)” is one of the well-adopted transforming methods exploited for compressing images. The extremely deployed version of DWT is convolution-oriented. Nevertheless, the lifting-oriented DWT scheme requires more contemplation on more proficient performance and lesser computation cost. This paper intends to propose a deep learning-based image compression model with a lifting scheme for predicting high-frequency subbands. Moreover, the fine-tuning in lifting factorization is done by a new Sea Lion with Averaged Update Evaluation that includes new cosine estimation under the COordinate Rotation DIgital Computer algorithm. Similarly, this study defines a new single objective function that merges the multiconstraints, like, “Peak Signal to Noise Ratio (PSNR) and Compression Ratio (CR)”. At last, the supremacy of the presented approach is proved with respect to varied measures, like, CR, PSNR and so on.

A new radiation-hardened architecture for holographic memory address calculation

Architectures for the memory address calculation unit of a holographic memory device have been deeply analyzed in the literature. Finite-precision analysis and the selection of parameters to ensure a discrepancy between the hologram plane and the observation plane of less than 1% has been performed by other designers. However, a fault-tolerant architecture implemented on field-programmable gate array (FPGA) for an Optically Reconfigurable Gate Array has not been proposed yet. Due to the importance of this unit in environments with high levels of radiation, such as robots in nuclear disasters or satellites in space, which are the most common applications, there is a real interest in protecting this hardware. This work introduces two main contributions: i) replaces the calculation of distances through a Coordinate Rotation Digital Computer (CORDIC) unit in order to save area and ii) improves the ratio of fault-detection and extends the input range of the trigonometric computations to exploit more efficient error detection techniques. The derived architecture allows us to recover the FPGA from a faulty behavior in 95% of the cases, which avoids waiting for slower processes such as scrubbing. This real-time detection only requires an extra area of 13% with respect to the unprotected circuit and does not include any loss of precision compared to previous designs.

Design and Implementation of a Wearable Accelerometer-Based Motion/Tilt Sensing Internet of Things Module and Its Application to Bed Fall Prevention.

Accelerometer-based motion sensing has been extensively applied to fall detection. However, such applications can only detect fall accidents; therefore, a system that can prevent fall accidents is desirable. Bed falls account for more than half of patient falls and are preceded by a clear warning indicator: the patient attempting to get out of bed. This study designed and implemented an Internet of Things module, namely, Bluetooth low-energy-enabled Accelerometer-based Sensing In a Chip-packaging (BASIC) module, with a tilt-sensing algorithm based on the patented low-complexity COordinate Rotation DIgital Computer (CORDIC)-based algorithm for tilt angle conversions. It is applied for detecting the postural changes (from lying down to sitting up) and to protect individuals at a high risk of bed falls by prompting caregivers to take preventive actions and assist individuals trying to get up. This module demonstrates how motion and tilt sensing can be applied to bed fall prevention. The module can be further miniaturized or integrated into a wearable device and commercialized in smart health-care applications for bed fall prevention in hospitals and homes.

Low-Latency Hardware Implementation of High-Precision Hyperbolic Functions Sinhx and Coshx Based on Improved CORDIC Algorithm

CORDIC algorithm is used for low-cost hardware implementation to calculate transcendental functions. This paper proposes a low-latency high-precision architecture for the computation of hyperbolic functions sinhx and coshx based on an improved CORDIC algorithm, that is, the QH-CORDIC. The principle, structure, and range of convergence of the QH-CORDIC are discussed, and the hardware circuit architecture of functions sinhx and coshx using the QH-CORDIC is plotted in this paper. The proposed architecture is implemented using an FPGA device, showing that it has 75% and 50% latency overhead over the two latest prior works. In the synthesis using TSMC 65 nm standard cell library, ASIC implementation results show that the proposed architecture is also superior to the two latest prior works in terms of total time (latency × period), ATP (area × total time), total energy (power × total time), energy efficiency (total energy/efficient bits), and area efficiency (efficient bits/area/total time). Comparison of related works indicates that it is much more favorable for the proposed architecture to perform high-precision floating-point computations on functions sinhx and coshx than the LUT method, stochastic computing, and other CORDIC algorithms.

Performance Analysis of Clock Gated Coordinate Rotation Digital Computer Based Least Mean Square Filter Design for Video Processing Applications

Design of a low power FIR filter has always been an area of intense research concern. Application of Co-ordinate Rotation digital computer (CORDIC) algorithm for designing a low power FIR filter is presented in this paper. CORDIC algorithm helps in the computation of complex trigonometric functions by using shift and adds mechanisms avoiding the need for a separate processor in hardware implementation. The challenge of noise interruption in real time video signal capturing is rejected greatly by using CORDIC LMS filter architecture. Also the area, power, and delay of the LMS filter are reduced to a good extent because of CORDIC multipliers. When compared to the previously discussed filter techniques in various works, the proposed technique shows 21.13% reduction in delay and 90.28% decrease in leakage power. Further improvement in dynamic power savings is obtained through clock gating technique applied to the sequential elements in the circuit, which reduces dynamic power dissipation by 70% from the previous works. The comparative study of benchmark filters with their specifications is presented with a detailed analysis of area, delay, leakage, and dynamic power. The video processing using CORDIC LMS filter is verified with MATLAB R 2021A software. The hardware implementation of the proposed architecture is done on a SPARTAN 3E FPGA kit with Xilinx ISE design suite interface. The design is also verified for delay, area, leakage, and dynamic power using CADENCE with GPDK 180 nm library.

Fast IQ Amplitude Approximation Method for ASIC Digital System

In some modules of digital systems, such as Fast Fourier Transform (FFT), Discrete Fourier transform (DFT), IQ (in-phase and quadrature components) modulation/ demodulation, the outputs use the complex data formed , and the calculation of its magnitude value √ are required. In software digital signal processing platform, the multiplication and square root operations are executed by using its math library; however, in Application specific integrated circuit (ASIC) digital system design, the implementation of those operators via Coordinate Rotation Digital Computer (CORDIC) algorithm requires the numerous resources and delays. So, in this paper, we present a fast approximation method for above problem which takes a small delay but acceptable accuracy for AISC digital system design. Keywords—ASIC, Digital system design, FFT, DFT, Fast amplitude approximation, Max-Min approximation.

Exploring the CORDIC Algorithm and Clock-Gating for Power-Efficient Fast Fourier Transform Hardware Architectures

This work explores hardware-oriented optimizations for the CORDIC (COordinate Rotation Digital Computer) algorithm investigating the power-efficiency improvements employing N-point Fast Fourier Transform (FFT) hardware architectures. We introduced three hardware-oriented optimizations for the CORDIC: (a) improving the signal extension, (b) removing the angle accumulation and (c) eliminating the redundancies in the iterations, both unnecessary when processing the FFT processing. Fully sequential FFT architectures of 32, 64, 128, and 256 points were synthesized employing ST 65 nm standard cell libraries. The results show up to 38% of power savings on average when using our best CORDIC optimization proposal to the FFT architecture comparing to the explicit multiply-based butterfly version. Moreover, when combining our best CORDIC optimization with the clock-gating technique, the power savings rises to 78.5% on average for N-point FFT.

Low-Complexity High-Precision Method and Architecture for Computing the Logarithm of Complex Numbers

This paper proposes a low-complexity method and architecture to compute the logarithm of complex numbers based on coordinate rotation digital computer (CORDIC). Our method takes advantage of the vector mode of circular CORDIC and hyperbolic CORDIC, which only needs shift-add operations in its hardware implementation. Our architecture has lower design complexity and higher performance compared with conventional architectures. Through software simulation, we show that this method can achieve high precision for logarithm computation, reaching the relative error of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-7</sup> . Finally, we design and implement an example circuit under TSMC 28nm CMOS technology. According to the synthesis report, our architecture has smaller area, lower power consumption, higher precision and wider operation range compared with the alternative architectures.

Fast hardware-oriented algorithm for 3D positioning in line-of-sight and single bounced non-line-of-sight environments

The ability to find the location of a mobile object and track it in two-dimensional (2D) and three-dimensional (3D) space is an indispensable feature of wireless communication systems. In particular, the increase in demand for using self-navigation technology in unmanned vehicles is attracting additional attention to this area of research. The methods and techniques developed for these systems compete in terms of simplicity, performance, and accuracy. However, the majority of solutions focus on only one of these performance metrics and are not applicable to the projected systems. In this study, a new location estimation solution that satisfies all three performance metrics (simplicity, accuracy, and efficiency) is achieved. The developed algorithms can be executed on a mobile object to allow it to learn its position in space. Furthermore, the simplicity of the mathematical operations used, namely binary shift and add operations, makes our algorithm hardware-friendly. Accelerated coordinate rotation digital computer (CORDIC) algorithms are used for the first time with line-of-sight (LOS) and single-bounced-scattering non-line-of-sight (SBS NLOS) signal arriving approaches for mobile object self-positioning. This study also introduces a newly developed 'vector-breaking' method (VBM) to estimate the location of a mobile object using the arriving signals from scatters with unknown locations. Test results using the developed algorithm show that the projected level of accuracy has been achieved. Furthermore, the developed algorithm performs better than the solutions currently available in the field.

PWL-Based Architecture for the Logarithmic Computation of Floating-Point Numbers

In this brief, we propose a logarithmic converter for floating-point numbers based on the piecewise linear (PWL) approximation method. The proposed method is applicable to any customized floating-point format with a mantissa length of 16–23 bits and a maximum absolute error (MAE) larger than 10−6. The logarithmic function is automatically segmented into several maximal subsections by a software-based segmentation scheme with the restriction of a predefined MAE and a fractional word length for the computing units. Then, we make a tradeoff between the piecewise number and the fractional word length. Based on the results of the segmentor, our design is coded in the Verilog hardware description language. The synthesized results show that our design consumes less area, time, and power without compromising accuracy compared to existing techniques based on the COordinate Rotation Digital Computer (CORDIC) and PWL methods.

WITHDRAWN: CORDIC algorithm for fixed point

For real numbers, there are two kinds of displays, which are stationary and floating. Based on their field for 16-bit, 24-bit, and 32-bit fixed point numbers, this document compared the initial CORDIC for sine–cosine generation. Floating point representation has the advantage of fixing-point representation (and integer) because it supports a broader variety of values and accuracy. An original CORDIC is also synthesized and results comparable for sine cosine generation in 24-bit, 28-bit and 32-bit floating point numbers. The use of 16-bit, 24-bit or 32-bit fixed point proposed a 64 bit fixed point CORDIC algorithm.

Efficient Design of Spiking Neural Network With STDP Learning Based on Fast CORDIC

In emerging Spiking Neural Network (SNN) based neuromorphic hardware design, energy efficiency and on-line learning are attractive advantages mainly contributed by bio-inspired local learning with nonlinear dynamics and at the cost of associated hardware complexity. This paper presents a novel SNN design employing fast COordinate Rotation DIgital Computer (CORDIC) algorithm to achieve fast spike timing–dependent plasticity (STDP) learning with high hardware efficiency. In this study, a system design and evaluation method of CORDIC-based SNN is proposed for finding optimal CORDIC type and precision, from theoretical CORDIC-level error to application-level learning performance. From the proposed design and evaluation method, a reconfigurable SNN design based on fast-convergence CORDIC is designed to achieve high classification accuracy on MNIST, fast on-line learning and good energy efficiency. By utilizing SNN’s fault tolerance and time-division-multiplexing (TDM) strategy, the reconfigurable SNN design employs 8-bit fast-convergence CORDIC and TDM-based hardware accelerator for high efficiency. FPGA implementation results confirm that the proposed fast-convergence CORDIC SNN design outperforms the state-of-the-art CORDIC method by 38.5%−45.3% in terms of learning speed and energy efficiency, with the STDP learning of 30.2 ns/SOP, energy efficiency of 176.6 pJ/SOP, processing speed of 6.1 ms/image, and on-line learning convergence of 21.4 s (time to reach the final accuracy, on average), on MNIST benchmark.

LSTM Cell Implementation on FPGAs

This paper presents and discusses the implementation of an LSTM cell on an FPGA with an activation function inspired by the CORDIC algorithm. The realization is performed using both IEEE754 standard and 32-bit integer numbers. The case with floating-point arithmetic is analyzed with and without DSP blocks provided by the Xilinx design suite. The alternative implementation including the integer arithmetic was optimized for a minimal number of clock cycles. Presented implementation uses xc6slx150t-2fgg900 and achieves high calculations accuracy for both cases.

LabVIEW-FPGA-Based Real-Time Data Acquisition System for ADITYA-U Heterodyne Interferometry

Microwave interferometry has been used extensively for plasma diagnostics in tokamak for real-time electron density measurements. Real-time density measurement is an indispensable part of advanced tokamaks, as it can be used as feedback to control the plasma operation. In this article, we report the development of the phase extraction method in a heterodyne interferometer for real-time density estimation using a field-programmable gate array (FPGA). FPGA provides parallel processing, minimum control delay, more efficient processing architecture, and jitter-free synchronization between different control layers. Digital CORDIC algorithm is used for the estimation of the phase between two arms of the interferometer. A LabVIEW program is developed for the FPGA target and host controller to acquire the data and estimate electron density in real time, which can be used for feedback purpose by regulating the amount of gas injection using piezoelectric valve that requires a high voltage (~100 V) for about 1 ms. The delay in generating the feedback signal is proportional to the sampling speed (100 kHz) of the analog signal. In this work, line-averaged electron density measurement using digital signal processing (DSP) and LabVIEW-FPGA technology is presented. The developed interferometer and data acquisition (DAQ) system installed on ADITYA-U tokamak can measure the electron density in the range of $1 \times 10^{18} - 1 \times 10^{20}\,\,\text{m}^{-3}$ . The algorithm used for the estimation of phase difference is validated using a conventional arctan method. The developed reconfigurable FPGA-based DAQ system uses low power, has a reconfigurable hardware structure for fast real-time signal processing, and can be easily upgraded.

Research and design of digital unit for direct digital frequency synthesizer

The direct digital frequency synthesizer (DDS) is a new kind of all digital frequency synthesizer, which has fast frequency switching speed and high frequency resolution. It has been widely used in the field of signal processing. In this article, we analyze the basic principle of DDS and study several methods of phase-amplitude conversion. We use the method of searching ROM table for rough rotation and the optimized CORDIC algorithm based on excess-fours structure for fine rotation to achieve the phase to amplitude conversion. The power consumption and area of the fine rotation element are reduced with the preprocessing of the phrase. The output frequency is increased by using a 4-channel-interpolation structure. After the design is completed, we verify its correctness and evaluate its performance. The results show the phase-amplitude conversion algorithm meets the need of correctness and the DDS can work stably at 1GHz.

VLSI Implementation of a Cost-Efficient Loeffler DCT Algorithm with Recursive CORDIC for DCT-Based Encoder

This paper presents a low-cost and high-quality, hardware-oriented, two-dimensional discrete cosine transform (2-D DCT) signal analyzer for image and video encoders. In order to reduce memory requirement and improve image quality, a novel Loeffler DCT based on a coordinate rotation digital computer (CORDIC) technique is proposed. In addition, the proposed algorithm is realized by a recursive CORDIC architecture instead of an unfolded CORDIC architecture with approximated scale factors. In the proposed design, a fully pipelined architecture is developed to efficiently increase operating frequency and throughput, and scale factors are implemented by using four hardware-sharing machines for complexity reduction. Thus, the computational complexity can be decreased significantly with only 0.01 dB loss deviated from the optimal image quality of the Loeffler DCT. Experimental results show that the proposed 2-D DCT spectral analyzer not only achieved a superior average peak signal–noise ratio (PSNR) compared to the previous CORDIC-DCT algorithms but also designed cost-efficient architecture for very large scale integration (VLSI) implementation. The proposed design was realized using a UMC 0.18-μm CMOS process with a synthesized gate count of 8.04 k and core area of 75,100 μm2. Its operating frequency was 100 MHz and power consumption was 4.17 mW. Moreover, this work had at least a 64.1% gate count reduction and saved at least 22.5% in power consumption compared to previous designs.

Multi-chord IR-visible two-color interferometer on KSTAR.

Major parts of an IR-visible two-color interferometer (TCI) on KSTAR have been upgraded for the multi-chord operation: (1) a diode-pumped-solid-state (DPSS) laser (660nm) replacing the former HeNe laser (633nm), (2) vacuum-compatible vibration isolator with titanium retro-reflectors, and (3) full digital phase comparator for multi-chord real-time density signals. The commercial compact DPSS laser suits the multiple chord configuration with its strong beam power (500 mW) and long coherent length (>100 m). Ti retro-reflectors are mounted on vacuum-compatible vibration isolators. The isolators are essential for the visible beams to avoid any fringe skips due to their short wavelength, considering the speed of the mechanical vibration (up to hundreds of μm). Field-programmable-gate-array (FPGA) modules count the entire fringes fast enough with a signal output rate up to 1.25MHz, solving the fringe skip issues. The FPGA module enables the full digital processing of the phase comparator with a CORDIC algorithm after the sampling rate of 160 MS/s for the 40MHz intermediate frequency of each beam. The full digital signals are transferred to the main plasma control system in real-time. Stable single-input-single-output operation of the KSTAR density control was demonstrated with the TCI. The real-time density profile control is also promising in the near future, with multiple actuators such as pellets and gas puffings.

Implementation of FPGA design of FFT architecture based on CORDIC algorithm

ABSTRACT The coordinate rotation digital computer (CORDIC) is a class of shift-add algorithm for the rotation of vectors on a plane. The major problem in this CORDIC algorithm is the linear rate of convergence with the speed of the iteration. The main aim of the improved CORDIC algorithm is to utilise an integrated adder subtractor in place of binary adder subtractor to decrease the count of iterations and hardware reduction technique. The improved CORDIC splits the rotation angle into several series of micro-rotation angles to calculate the rotation and the new set of angle provides a fast convergence. The canonical signed-digit (CSD) approach together with Hcub algorithm employs for the number of adder subtractor reduction and shifters in CORDIC architecture design. The performances of the proposed CORDIC design have been verified by employing it in FFT implementation. The simulation result indicates the higher frequency of 77.20%, 82.78%, 78.30% and 76.57% when compared with conventional methods. The evaluation of FFT is also done by comparing with the conventional methods. The power consumption, number of iterations and the hardware complexity reduced by using the improved CORDIC and the working of this proposed algorithm is evaluated through the FPGA implementation.