Copper Redistribution Layer Research Articles

Next Level of 1/1 μm Line and Space Copper Redistribution Layer Fabrication with Organic Dielectric Materials

An electrical reliability of fine copper redistribution layer (RDL) with 1/1 μm line and space fabricated by using positive photosensitive polyimide (PSPI) has been demonstrated. The polyimide containing flexible molecular units in PSPI was introduced, in assumption to increase the entanglement of each polymer chain with a design concept of polymer backbone to enhance mechanical and thermal reliability. To conduct a series of tests, test vehicles with semi-additive copper RDL with 1/1 μm line and space were fabricated with Toray’s PSPI for electrical reliability test. Through a series of electrical reliability tests utilizing our test vehicles, PSPI out-performed the phenol-based resin, which has been proven to have excellent mechanical and thermal stabilities when compared with other resins. 1/1 μm line and space electrodes after electrical reliability tests were also observed and cross-sectioned. The observation of electrodes clearly showed oxidation-reduction of the electrodes on anode and cathode, respectively. On the cathode, copper particles of several nm in diameter were formed on the PI film surrounding the copper wiring. On the anode, copper oxide layers of about 100 nm thickness were observed on the copper wiring surface, which turned out to be Cu2O when analyzed with Electron Energy-Loss Spectroscopy (EELS) measurement.

(Invited) Micro-Transfer-Printing: A Novel Technology for Volume D2W Integration

In the past decade, the semiconductor industry has witnessed an ever-increasing demand in wafer-level integration and packaging technologies driven by increased requirements on functionality, performance, and efficiency. As one of the world’s leading specialty foundry groups for analog/mixed semiconductor technologies and more than thirty years of experience in volume manufacturing for automotive, industrial and medical applications, the X-FAB group has recognized this trend and broadened its offer accordingly. New integration techniques like wafer bonding, through-passivation vias (TSVs) processing, redistribution layers (RDLs) as well as the readiness to introduce new material systems like glass, polymers, noble metals, or compound semiconductors in a CMOS manufacturing environment clearly highlight the ongoing transformation process.Next to the stated, also Die To Wafer (D2W) integration technologies receive an increased interest and represent one additional topic of these developments. Especially the Micro-Transfer-Printing technology (also referred as mass transfer or just transfer-printing) gained particular interest and has seen comprehensive developments over the past years.To enable a heterogeneous chip integration, the micro-transfer-printing technology utilizes elastomeric stamps (see Figure 1 a; gray) with tunable adhesive properties to transfers devices or arrays of devices (commonly referred to as chiplets) from their native substrate (source wafer, orange) to a non-native target material (blue). This integration approach does not only enable heterogeneous 3D-wafer-level integration, it also provides several benefits like: high potential throughput since thousands of chiplets can be transferred in a parallel manner by the elastomeric stamp,the possibility to integrate smallest-scale devices,the opportunity to effectively utilize expensive source wafers and to transfer chiplets to multiple devices or target wafers,the high placement accuracy of 3σ < 1.5 µm, andthe opportunity to package devices with extremely short metallization tracks. To offer this versatile technology, X-FAB has set-up a µTP pilot line for the development and industrialization of related processes in the MEMS clean room facilities in Erfurt, Germany.Enabling an integration as depicted in Figure 1a) requires the development of several dedicated process sequences that have to be applied to source (orange) and target wafer (blue) to: form chiplets that are appropriate for integration via µTP, i.e. the source wafer has to be made “print-ready”,enable a high adhesion and thereby high print yield by adding a dedicated adhesion layer on the target wafer, andallow wiring and passivation of the integrated devices by subsequent adhesion patterning, redistribution layer (RDL) formation and passivation layer deposition. Out of the variety of potential integration option and material systems, X-FAB decided to focus on basically two integration scenarios, namely i) the preparation of print-ready SOI-based CMOS ASICs and ii) heterogeneous integration on CMOS wafers which both shall be explained in more detail within this presentation.The general process to make devices print-ready involves the chiplet singulation by multiple dry etches to form trenches down to handle wafer bulk material,the tether formation by SixNy deposition and patterning to form a mechanical system that holds the chiplet in place andthe wet chemical release etch to separate the singulated µIC from the handle wafer. Thereby, a print-ready µASIC is formed. It refers to a state in which the IC is separated from its original handle wafer and just kept in place by the tether systems as shown in Figure 1b. A basic requirement for the development of this process is the use of an SOI technology (such as X-FAB’s XT018), since the buried oxide layer (BOX) acts as the chiplet bottom protection in the final release etch.Next to the scope of providing X-FAB’s µASICs for an integration via transfer-printing, X-FAB is actively working on the assembly of III/V semiconductor elements/chiplets on CMOS ICs/ wafers to improve the performance of the available CMOS devices or even add new functionality. Based on the availability of print-ready III/V semiconductor chiplets provided by X-FAB’s foundry partners, the integration process involves the deposition of an adhesive layer on top of the CMOS wafer surface,the transfer-printing integration of the III/V chiplets,the final curing of the adhesive layer to adjust the material properties,the patterning of the adhesive by a dry etching process to open the CMOS wafer contact pads,the subsequent formation of a copper redistribution layer (RDL) andfinally, the passivation of the formed wafer-level package to protect the integrated chiplet and the metallization layer from environmental influences. An example of such an integrated wafer-level package (without passivation) is illustrated in Figure 1 c). Figure 1

Micr -Transfer Printing for Efficient 3DHI of 100-300mm Wafers and Glass Panels

This paper presents an analysis of using micro-transfer printing (MTP) for three-dimensional heterogeneous integration (3DHI) of diverse components made using 100mm, 200mm and 300mm wafers with large area glass substrates. Techniques for achieving high throughput and high wafer and substrate utilization, despite their size mis-matches, are described in detail along with MTP’s pros and cons versus alternative wafer-to-wafer and die-to-wafer 3DHI technologies. MTP, a massively parallel pick-and-place process, efficiently transfers large arrays of ultra-thin (&lt;10 micron), small, diverse components (“x-chips”) from one or more source wafers to destination substrates. MTP enables disruptive 3DHI of compound semiconductors, including GaN, GaAs, InP, SiGe and emerging materials, silicon and passive components for wireless and optical communications, power management, sensor, photonics and other analog / mixed signal applications. Since the x-chips are ultra-thin and active side up, standard copper redistribution layer (RDL) technology may be readily used to interconnect the x-chips and destination die, resulting in very short path lengths and, hence, minimum parasitics. ASM AMICRA and X Display Company supply R&amp;D and production MTP manufacturing systems. More than twenty MTP systems are installed worldwide at X-FAB, Micross Components, Tyndall National Institute, Teledyne, the Naval Research Laboratory, the University of Illinois Urbana Champaign, the University of Ghent / imec, UPVfab and undisclosed leading manufacturers.

Effect of Titanium-Polymer Interactions on Adhesion of Polymer-Copper Redistribution Layers in Advanced Packaging

The ever-increasing demand for high-bandwidth interconnects has given rise to the need for high IO-density package redistribution layers (RDL). This necessitates scaling down RDL critical dimensions. There are numerous challenges pertaining to the further miniaturization of polymer RDL. The main challenge is the adhesion of copper RDL to the polymer dielectric. The chemical interactions between polymer and metal seed-layer play an important role in adhesion. This paper presents the study of chemical interactions between titanium and various commercial polymer dielectrics using XPS and FTIR spectroscopy. The effects of pre-deposition processes on chemical interactions and thereby adhesion strength are investigated. It was observed that the chemical interactions between titanium and polymer can be improved by plasma processing leading to a significant enhancement in adhesion strength. In case of ABF dielectric, the mean adhesion strength was increased from 8.9 N/cm to 10.8 N/cm. This adhesion enhancement was attributed to the formation of larger number of Ti-C bonds between the titanium seed and the polymer backbone. XPS and FTIR analyses are presented to elucidate the mechanism of adhesion enhancement.

Warpage Analysis and Prediction of the Advanced Fan-Out Technology Based on Process Mechanics

Moore’s law has remarkably promoted the development of semiconductor technology over the last decades. The advanced packaging involving novel materials, structures, and processes has contributed significantly to achieving excellent performance. Among various forms of advanced packaging, wafer-level-fan-out packaging is superior to standard wafer-level packaging in that it allows more input/output (I/O) connections, leading to landmark development for high-end devices. Furthermore, fan-out wafer-level package (FOWLP) technology enables heterogeneous integration of chiplets fabricated with different manufacturing processes, which provides integrated, sophisticated, and multifunctional dies with higher performance, lower cost, and tinier size. In packaging materials, processes, and structures, a thorough understanding of the process mechanics is necessary to ensure accuracy, while multiphysical field and multiscale modeling are beneficial to clarifying the internal mechanism of warpage. Process mechanics was applied to FOWLP and the characteristics were systematically expounded. Focusing on the warpage analysis of the embedded silicon fan-out (FO) wafer-level package, we introduced the principle of process mechanics and explored the material–structure–process interaction. The typical processes (including: 1) cleaning and litho cavity; 2) die attach and assignment; 3) dry film and dielectric layer 1 and patterning; 4) physical vapor deposition (PVD) seed layer 1 and patterning copper plating and redistribution layer (RDL) 1; 5) dielectric layer 2 and patterning; 6) PVD seed layer 2 and patterning copper plating and RDL 2; and 7) passivation layer, drop ball back grinding, and dicing) of the embedded silicon FO packaging are analyzed in detail to explore the warping evolution of individual processes. In addition, a material equivalent model of representative volume element (RVE) and an extended theoretical model of a multilayer structure were proposed. The comprehensive comparison for the extended theoretical model, experimental measurement, and finite element model (FEM) showed that the theoretical model is effective and relatively accurate. Overall, both the theoretical model and FEM are feasible approaches for predicting the warpage during the manufacturing process.

Effect of oxidation on electromigration in 2-µm Cu redistribution lines capped with polyimide

Polyimide (PI) has been adopted to protect the Cu from oxidation in the packaging industry. Electromigration (EM) of Cu redistribution layers (RDLs) capped with PI was investigated at 160 °C under 1.0 × 106 A/cm2. The results indicated that failure of fine-pitched (2-µm) is different from that of 10-µm RDLs, which is void formation. The failure of the 2-µm RDLs is mainly caused by severe oxidation during EM. To analyze the EM failure of the Cu RDLs with different pitches, the oxidation area of nanotwinned copper (nt-Cu) and regular Cu RDLs during EM was compared. We propose an oxidation equation to estimate the resistance increase of RDLs with various widths.

Semi-empirical law for fatigue resistance of redistribution layers in chip-scale packages

In this work we present a semi-empirical law for the fatigue resistance of redistribution layers (RDLs) in chip-scale packages. Fatigue of the copper RDL can lead to cracks in the RDL stack, which might eventually propagate into the die causing catastrophic electrical failure. In order to derive a semi-empirical law for RDL fatigue, the mechanical response of several test vehicles that showed this failure mode during temperature cycling tests have been simulated. The computed accumulated inelastic strain energy density in the RDL at the failed location shows a power-law dependence with the onset of fail found experimentally. The results show that the onset of fail does not scale with the package dimensions, as the RDL design itself plays a significant role. Furthermore, the design of the PCB is shown to have a dominant influence as well. To substantiate these experimental findings, micron-scale test coupons, consisting of representative copper traces on silicon wafers, were specially designed and fabricated in this study for investigation of the cyclic fatigue durability of RDL copper. The characteristic dimensions of the copper traces were selected to be comparable to those in RDLs. However, the fatigue resistance of these Cu-on-Si test coupons is significantly higher than that of RDL traces in actual applications. Therefore, we conclude that the semi-empirical law can be used for predictive modeling of the onset of RDL fail, only if a representative pool of test vehicles has been considered. More fundamental research is still needed to gain a complete understanding of the failure mechanism.

Photosensitive Glass-Ceramics for Heterogeneous Integration

The push for heterogeneous integration requires very unique material properties with respect to processing, material constants, and integration capabilities with other materials (such as copper, II...

Productivity Comparison of Wafer Transport Architectures in PVD Tools Used for Fan-Out Packaging RDL Barrier/Seed Formation

Abstract Physical Vapor Deposition (PVD) systems are widely used in the semiconductor fabrication industry, both for front-end applications in the wafer fab and for back-end applications at device packaging houses. In fan-out wafer level packaging (FOWLP), and in fan-out panel level packaging (FOPLP), sputter deposited Ti and Cu are the base on which electroplated copper Redistribution Layers (RDLs) are built. For these RDL barrier/seed layers, PVD cluster tools, wafer transport architectures that have been widely used since the mid-1980s, are the current Process of Record (POR) in advanced packaging; however, these tools typically operate in a regime where wafer transport is robot-limited to approximately 50 wafers per hour, which limits overall throughput and greatly influences Cost of Ownership (COO) for the sputter deposition step(s), because the central handling robot occupied with a transfer from the Ti PVD module to the Cu PVD module, for example, has no opportunity to be doing anything other than that specific transfer. Other wafer transport architectures are more efficient from a wafer handling perspective. In linear transport carrier-based PVD tools, wafers or panels passing through the system benefit from a mechanical transfer time budget that is considerably less than for a cluster tool. Transport time overhead per wafer on linear transport systems is quite low, and scheduler software optimization becomes less onerous too, as a result of the simpler wafer transport architecture. We analyzed the relative throughput of cluster and linear transport PVD tools for a typical FOWLP barrier/seed layer (1000Å Ti / 2000Å Cu) sputter deposition process, and present details here of how the time spent moving wafers to various processing chambers affects overall system productivity. In the case of the cluster tool architecture, with its central wafer handling robot, wafer throughputs are approximately 50 wafers per hour, while on the linear transport system wafer throughputs as high as 240 wafers per hour are possible. The significant difference in system throughputs greatly affects the relative Cost of Ownership (COO) per wafer processed, with the linear transport system returning COO results that are less than half those of the typical cluster PVD tool.

Challenges in Assembly implementation of ultra-thin profile flipchip package-on-package

Abstract The assembly and structural challenges associated with a low profile bare die flipchip package-on-package (PoP) are reviewed. The PoP was designed to accommodate a JEDEC 256 ball FBGA memory. This dual channel 32-bit LPDDR3 memory package has a unique signal crossing ball arrangement between the Data bus of one channel and the Control/Address (CAS) bus of the other. The ball arrangement presents some crossing challenges for PoP implementation of controller ICs. For timing reasons, the memory controller blocks are traditionally placed together in a central area of the base chip, and signals are routed to line up with the fixed LPDDR3 landing sites. For the dual channel case the routing requires crossing one CAS signal group over the other's data lines. To address this crossing in this product, a copper redistribution layer (RDL) was deployed at the bump stage to bring the appropriate LPDDR3 signals from the controller block to line up with the memory balls. The thick copper RDL/Cu-Pillar arrangement left a 10–13um of dielectric layer over the base die. Because the 0.4mm pitch and clearance requirements of the selected memory package, a very low profile flipchip die standoff was required. The dielectric layers and copper density in RDL had significant impact on the handling of these thinned wafers and die through the assembly processes. Though newer package offerings - like Amkor's Thru Mold Via (TMV) technology or Invensas' Bond Via Array (BVA could have been deployed, a Cu-pillar based bare die flipchip (FCBGA) using a very thin die was selected for its simplicity and lower cost. All package related reliability tests have been completed with success. The process optimization and trade-off needed to achieve success through assembly are discussed in this paper

Analysis of Oxidized Copper Surface and its Evolution

The interest towards Copper RDL (Re-Distribution Layer) is due to some advantages related to this approach. First of all it is cheaper than conventional Damascene approach; moreover it allows thicknesses as high as 10µm or more whereas with Damascene architecture Cu thickness is limited to &lt;5µm. Figure 1 introduces the architecture concept, which is based on a quite long ECD growth on a substrate with patterned PhotoResist.

Evaluation of Low Stress Photo-Sensitive Spin On Dielectric Layers for Through Silicon Via (TSV) Copper Redistribution Layers

To increase performance of semiconductor devices advances in packaging such as chip stacking (3D) and silicon carrier technologies (SoC) are being developed. Adaptation of these packaging fabrication methods offers the ability to incorporate functionality as well as provide memory and power distribution on one IC with increased signal bandwidth. An enabling element in both the stacking and silicon carrier technologies is through silicon vias (TSV) which electrically connect dies to a silicon carrier or via stacked chips (1). Creation of TSV involves via fabrication, wafer thinning and back side wafer finishing, to name a few, some of which are relatively new to semiconductor processing. Furthermore, because the wafer backside is accessible it can now be utilized to route wiring to further increase package density. The focus of this research was to evaluate photo-sensitive spin on dielectric materials (SOD) that can be used as the backside wiring levels, commonly referred to as redistribution layers (RDL) in TSV technologies. The two materials evaluated are; the epoxy based Dow INTERVIA™ 8023 Dielectric and the Benzocyclobutene (BCB) polymer, Dow CYCLOTENE™ 4000 product series. These dielectric materials have low stress and provide good planarization (2). Test vehicles with a chip size of 3.7 cm x 2.26 cm were fabricated with a 6 um wide copper RDL layer using the SOD materials of interest as well as conventional PECVD SiO2/SiN dielectric layers. The large chip size accommodated parallel Cu lines running 1.8 cm long with a spacing of 3 ï&amp;#x81;¬m and represented an aggressive shorting test for the SOD materials. It also enhances chip distortion after thinning and is evaluated for all three test vehicles. Chips were then electrically tested through simulated 260° C reflow cycles (for flip chip joining) and accelerated thermal reliability tests from −55° C to 125° C for 1000 cycles.