Challenges in Assembly implementation of ultra-thin profile flipchip package-on-package

Abstract

Abstract The assembly and structural challenges associated with a low profile bare die flipchip package-on-package (PoP) are reviewed. The PoP was designed to accommodate a JEDEC 256 ball FBGA memory. This dual channel 32-bit LPDDR3 memory package has a unique signal crossing ball arrangement between the Data bus of one channel and the Control/Address (CAS) bus of the other. The ball arrangement presents some crossing challenges for PoP implementation of controller ICs. For timing reasons, the memory controller blocks are traditionally placed together in a central area of the base chip, and signals are routed to line up with the fixed LPDDR3 landing sites. For the dual channel case the routing requires crossing one CAS signal group over the other's data lines. To address this crossing in this product, a copper redistribution layer (RDL) was deployed at the bump stage to bring the appropriate LPDDR3 signals from the controller block to line up with the memory balls. The thick copper RDL/Cu-Pillar arrangement left a 10–13um of dielectric layer over the base die. Because the 0.4mm pitch and clearance requirements of the selected memory package, a very low profile flipchip die standoff was required. The dielectric layers and copper density in RDL had significant impact on the handling of these thinned wafers and die through the assembly processes. Though newer package offerings - like Amkor's Thru Mold Via (TMV) technology or Invensas' Bond Via Array (BVA could have been deployed, a Cu-pillar based bare die flipchip (FCBGA) using a very thin die was selected for its simplicity and lower cost. All package related reliability tests have been completed with success. The process optimization and trade-off needed to achieve success through assembly are discussed in this paper