Development of low profile fan out PoP solution with embedded passive

Abstract

Currently PoP (Package on Package) has become a main stream of 3D integration for logic devices such as baseband and application processors with high performance memory in mobile application. This PoP has an advantage of a smaller package size with high functionality due to stacking of two different packages. However a conventional PoP with PCB substrate has a limitation to meet the recent requirement of a low profile with high performance in the thin mobile application. A fan out wafer level packaging is one of promising solution to meet a low profile with high performance. The direct solder attach on the RDL layer in the wafer level package provide a low profile package and RDL formation beyond Si die area provide a high performance with allowing higher solder ball counts. Also an embedded passive into fan out wafer level package is able to provide the better performance as well as flexibility to extend to SiP (System in Package). In this study, a low profile fan out Package on Package was successfully demonstrated with 14.0×14.0mm of a bottom package and 8.0×8.0mm of top package as well as embedded passives. The top and bottom package were electrically connected through TMV (Through Mold Via) with electro-less plating. TMV (Through Mold Via) was characterized with various EMC materials such as filler size, contents and resin material. The optimization of passive component location in term of process and reliability was performed using mold flow simulation. Also an assembly process was developed to minimize the package warpage using thermo-mechanical simulation.