Development of Package-on-Package Using Embedded Wafer-Level Package Approach

Abstract

The ever-increasing demands of higher performance, multiple functions, higher density, and lower cost mandate the reduction of the I/O pitch on the die as well as on the package. Pitch specifications of current substrate technologies do not match the stringent fine-pitch I/O requirements. Combining embedded wafer-level package (EMWLP) and package-on-package (PoP) technologies yields a preferred solution providing fan-out area to route the fine-pitch I/Os of the chip to large-pitch I/Os on to the extra area of fan-out EMWLP packages and allows the use of conventional substrate technology. However, there are many challenges to realizing the PoP of EMWLP packages. They include the die shift during the reconstruction process, double-sided reroute distribution line (RDL), and through-mold via (TMV) connections on a thin bottom package. The assembly of EMWLP and PoP, thermal management of PoP packages, and their reliability are also major concerns. This paper describes the development of an EMWLP PoP of 12 mm × 12 mm footprint with 432 I/Os and the adoption of TMV to enable PoP connections. The top package circuitry is accessed through TMVs in the bottom package with double-sided RDL. Solid TMV and side-wall-plated TMV are demonstrated in the EMWLP. Mechanical modeling of the PoP is conducted to optimize the structures of the packages for good reliability performance of the PoP. Thermal dissipation of the PoP is another area of concern, because the thermal path of the top package is limited in mobile applications. The thermal performance of the developed PoP was analyzed by thermal modeling and was successfully validated by thermal characterization of the PoP module. The developed PoP successfully passed the JEDEC standard reliability tests such as moisture sensitivity level 3 test; the unbiased highly accelerated stress test for 96 h, 500 air-to-air thermal cycling ( -40°C to 125°C), and 30 drop tests.