Copper Pillar Flip Chip Research Articles

Effects of Interconnect Shape and Thermal-Electro-Migration on Solder Creep of Copper-Pillar Flip Chip Joints

With the development of electronic products toward high density and high reliability, the size of interconnect solder joints and interconnect pitch continues to decrease. Under normal service conditions, solder joints are subjected to thermal–electric–mechanical loads simultaneously, resulting in reliability problems for many package structures. This article investigated the effects of interconnect shape and thermal-electro-migration on solder creep of copper-pillar flip chip joints and analyzed the corresponding failure modes and mechanisms. In this article, solder joints with different shapes were obtained by adjusting the thermal compression bonding process parameters, and creep experiments were performed on the solder joints under different temperature and stress conditions. In addition, we have performed thermoelectric coupling experiments and finite element simulations for different shapes of solder joints. Moreover, creep experiments were conducted on three types of solder joints after 10 and 40 h of thermoelectric coupling pretreatment. The results show that the three solder joints exhibit typical creep characteristics under different experimental conditions and the creep strain rate increases with the increase of shear stress and temperature. Under the same conditions, the creep strain rate of the hourglass-shaped solder joint is always higher than that of the other two solder joints. The electromigration reliability of the hourglass-shaped solder joint is the worst, and the electromigration reliability of the cylinder-shaped solder joint is the best. With the increase of thermoelectric coupling pretreatment time, the creep strain rate of solder joints increased significantly, and the fracture mode of solder joints gradually changed from ductile fracture to brittle fracture. Among the three types of solder joints, the creep resistance of the hourglass-shaped solder joints is greatly affected by the thermoelectric coupling pretreatment.

Fine-pitch Copper Pillar Flip Chips in High Reliability Applications

Abstract To keep up with the demands for smaller antennas with increased performance and decreased costs, most next generation architectures mandate higher IC (integrated circuit) chip integration. Compared to conventional packaging configurations, advanced chip packaging technologies, such as 2.5D and 3D, offer greater chip compatibility and lower power consumption. Given these advantages, the adoption of advanced packaging is inevitable. Within advanced packaging, the copper pillar interconnect is a key enabling technology, and the next logical step. This technology offers several benefits, including improved electromigration resistance, improved electrical and thermal conductivity, simplified underbump metallization (UBM), and higher I/O (input/output) density. The fine pitches that copper pillars allow helps the technology to supersede solder bump technology, which reaches its lowest pitch around 40 microns. Finer pitches allow for a higher I/O count, which increases performance. In this work, assembly of ultra-thin MMIC (monolithic microwave integrated circuit) GaN (Gallium Nitride) fine-pitch copper pillar flip chip assemblies on high density interposers was successfully demonstrated. Using 150μm pitch copper pillar flip chip, the assembly processes for both organic PCB (printed circuit board) and silicon interposers were evaluated, with both an ENIG (Electroless Nickel Immersion Gold) and eutectic tin-lead solder pad finish evaluated. For the 2D/2.5D/3D assembly process development, a standard in-house pick and place tool was used, followed by mass solder reflow, finished with an underfill for reliability test. The interconnect robustness was determined by die pull strengths, a flux stamping investigation, and cross-sections. Complete reliability and qualification test data on GaN copper pillar flip chip 2D assembly was completed, including 700 temperature cycles and UHAST (unbiased highly accelerated temperature/humidity stress test).

Empirical Equations for Optimization Conditions in Thermal Compression Bonding of Copper Pillar Flip Chip Packages

In this paper, finite element simulations are used to analyze the plastic deformation of the solder ball and its stress and strain distributions. The bonding forces that depend on the forming temperature are investigated. The contact areas between the solder ball and the copper trace are also discussed. The largest contact area is regarded as the optimization condition during the thermal compression bonding processes. The effects of different pillar-trace shift ratios on the contact areas are also discussed to provide a guideline for avoiding product failure. Finally, an empirical equation adopting a four-parameter logistic nonlinear regression model for the pillar-trace gap in terms of the forming temperature and bonding forces is established.

Warpage behavior analysis in package processes of embedded copper substrates

With the advance of the semiconductor industry and in response to the demands of ultra-thin products, packaging technology has been continuously developed. Thermal bonding process of copper pillar flip chip packages is a new bonding process in packaging technology, especially for substrates with embedded copper trace. During the packaging process, the substrate usually warps because of the heating process. In this paper, a finite element software ANSYS is used to model the embedded copper trace substrate and simulate the thermal and deformation behaviors of the substrate during the heating package process. A fixed geometric configuration equivalent to the real structure is duplicated to make the simulation of the warpage behavior of the substrate feasible. An empirical formula for predicting the warpage displacements is also established.

Metal fatigue in copper pillar Flip Chip BGA: A refined acceleration model for the aluminium pad cracking failure mechanism

The increasing complexity of automotive-oriented Application Specific Integrated Circuits (ASICs) pushed the industry to innovative packaging solutions that are sometimes challenged by the severe automotive quality targets. This study is related to the characterization of an advanced Flip Chip Ball Grid Array (FC-BGA) package with copper pillar interconnections, specifically to its reliability performance versus the Temperature Cycling (aligned to AEC-Q100 Grade 1 perimeter).The thermo-mechanical stress – due to the different Coefficients of Thermal Expansion (CTEs) of the materials in the system – is the root cause of a failure event never discovered before: cracked pads at the aluminium layer level, just below the Cu pillar, showing the symptoms of metal fatigue.Starting from the consolidated Coffin–Manson law, a refined acceleration model for this new failure mechanism is here proposed. It assumes the existence of a stress-free temperature range, which is defined as the portion of the entire thermal load that does not produce fatigue on the pillar stack. The stress-free temperature range hypothesis and the estimate of its extent were validated through a good fitting of the data coming from the experimental trials performed on the aforementioned copper pillar FC-BGA package.The model obtained was employed to allow a more accurate failure rate prediction for the studied Flip Chip package for automotive applications.

Numerical analysis of thermo-mechanical and mobility effects for 28 nm node and beyond: Comparison and design consequences over bumping technologies

Thanks to finite elements simulation and dedicated post-processing routines, this paper explores stress induced mobility changes over three major bumping processes. A numerical comparative analysis over the assembly generations is carried out. In order to do so, models are built for solder flip chip, copper pillar flip chip and micro-copper pillar bumping. Design recommendations for MOSFET placement to include in conception tools are provided, which allow to ensure adherence to product specifications while technologies advance.It is demonstrated that stress effects on mobility are widely dependent on the integration flow, and transistor placements must be considered accordingly. Despite the fact that, qualitatively speaking, the generated stress states are quite similar for whole bumping schemes, the quantitative variations of each stress components in combination with the piezo resistive coefficients of silicon lead to distinct effective mobility variations. As a consequence, design rules and keep out zones can be optimized specifically for each assembly technology. More precisely, it is advised to avoid nMOS placement directly below the bump in flip chip devices, for which the mobility can be degraded by almost 5%. In these cases keep out zones must be considered. Reversely, in the case of 3DICs, the performances of nMOS are improved by more than 2% in that region, which means that no restriction is required and silicon area can hence be saved. As for the p type carriers, variability is sensitive to channel orientation rather than their location with respect to the bump: more precisely, the transport direction must be azimuthally oriented, and radially oriented pMOS are proscribed. Maximum variations of about ±5% are found for the copper pillar flip chip configuration. Thanks to a comprehensive analysis, FEoL designers will be able to integrate BEoL and packaging constraints during the conception phases of advanced semiconductor products.

Thermal modeling approach for enhancing TCNCP process for manufacturing fine pitch copper pillar flip chip packages

Flip chip technology has traditionally been driven by electrical performance and package miniaturization, with application processors being primary drivers for devices like smart-phones and tablets. Today solder interconnect pitches, for both low-end and high-end flip chip applications, approximately range from 200μm to 90μm in area array. Advanced silicon nodes create challenges to fine pitch flip chip interconnects and corresponding substrate technology. Fine pitch (<60μm pitch) flip chip (FPFC) packaging is an emerging technology that meets the demand for both smaller form factors and lower cost products. Copper pillar bumps are best suited for fine pitch applications because they allow low standoff height and robust package reliability. Previous feasibility studies show that thermo-compression bonding process with non-conductive paste (NCP) is well suited for manufacturing copper pillar based FPFC packages because the NCP paste encapsulates the bumps and protects the vulnerable die interconnects. TCNCP process can be described as (1) NCP paste is pre-dispensed on a substrate (2) bumped die is picked up by the heater tool (3) proper heating profile and compression load is applied and (4) heater tool detaches and die is allowed to cool. This process requires precise control of temperature and force to get robust flip chip interconnect shape and void-free NCP coverage. TCNCP process has very small heating times usually ranging between 2 to 4 seconds per die. Within such short time, the heater temperature is quickly ramped up to 3 times its initial temperature to melt the solder at the tip of the copper bumps and cure the NCP. Small package layers make it very difficult for the heat to spread quickly. Therefore any temperature gradients within the heater are propagated into the die. Large temperature gradients within the die can potentially introduce manufacturing related challenges like solder “non-wet” and “de-wet”. In this paper these issues are briefly discussed. An experimentally validated thermal model is presented to develop an understanding of rapid heat flow patterns during a typical TCNCP process. Detailed parametric computational study is performed on different die sizes, heating temperature and time to propose a broad guideline on achieving optimal temperature distribution during the TCNCP process.

Sputtering under ultrahigh vacuum environment : G. Peter, J. A. Koprio and R. Slepicka. Vacuum38(8–10), 795 (1988)

Thanks to finite elements simulation and dedicated post-processing routines, this paper explores stress induced mobility changes over three major bumping processes. A numerical comparative analysis over the assembly generations is carried out. In order to do so, models are built for solder flip chip, copper pillar flip chip and micro-copper pillar bumping. Design recommendations for MOSFET placement to include in conception tools are provided, which allow to ensure adherence to product specifications while technologies advance.It is demonstrated that stress effects on mobility are widely dependent on the integration flow, and transistor placements must be considered accordingly. Despite the fact that, qualitatively speaking, the generated stress states are quite similar for whole bumping schemes, the quantitative variations of each stress components in combination with the piezo resistive coefficients of silicon lead to distinct effective mobility variations. As a consequence, design rules and keep out zones can be optimized specifically for each assembly technology. More precisely, it is advised to avoid nMOS placement directly below the bump in flip chip devices, for which the mobility can be degraded by almost 5%. In these cases keep out zones must be considered. Reversely, in the case of 3DICs, the performances of nMOS are improved by more than 2% in that region, which means that no restriction is required and silicon area can hence be saved. As for the p type carriers, variability is sensitive to channel orientation rather than their location with respect to the bump: more precisely, the transport direction must be azimuthally oriented, and radially oriented pMOS are proscribed. Maximum variations of about ±5% are found for the copper pillar flip chip configuration. Thanks to a comprehensive analysis, FEoL designers will be able to integrate BEoL and packaging constraints during the conception phases of advanced semiconductor products.