Warpage behavior analysis in package processes of embedded copper substrates

Yeong‐Maw Hwang ,Tsang-Hung Ou,Wei‐Hung Su

doi:10.1051/matecconf/201712300014

Yeong‐Maw Hwang , Tsang-Hung Ou + Show 1 more

Open Access

https://doi.org/10.1051/matecconf/201712300014

Copy DOI

Abstract

With the advance of the semiconductor industry and in response to the demands of ultra-thin products, packaging technology has been continuously developed. Thermal bonding process of copper pillar flip chip packages is a new bonding process in packaging technology, especially for substrates with embedded copper trace. During the packaging process, the substrate usually warps because of the heating process. In this paper, a finite element software ANSYS is used to model the embedded copper trace substrate and simulate the thermal and deformation behaviors of the substrate during the heating package process. A fixed geometric configuration equivalent to the real structure is duplicated to make the simulation of the warpage behavior of the substrate feasible. An empirical formula for predicting the warpage displacements is also established.

Highlights

Thermal bonding of copper pillar flip chip packages is a relatively new bonding process in packaging technology field, especially for a substrate with an embedded copper trace
The final goal of this study is to reduce the warpage behavior as much as possible, so the maximum deformation value in thickness direction(Y) of the substrate was selected as the quality characteristic, type of Smaller-the better quality characteristic is adopted in this study
To establish a simpler layout, an area occupation ratio is used to construct the complicated configurations of copper traces M1 and M2 layers

Summary

Introduction

Thermal bonding of copper pillar flip chip packages is a relatively new bonding process in packaging technology field, especially for a substrate with an embedded copper trace. During the heating package process of an embedded copper trace, the substrate warps at high temperatures as shown in Fig.1 [1]. Kim et al [2] used an anisotropic shell model, considering their viscoelastic properties, to simulate the warpage behavior of a high-density multilayer printed circuit board for solid-state disk drive, with homogenized copper patterns. Both the maximum warpage and the residual warpage of the full microelectronic package were predicted. The methodology accounted for both the trace pattern planar density and planar orientation in material property calculations for each layer of a multilayer substrate. Their results using the developed methodology agreed with the experimental data

Objectives

Results

Conclusion