Damascene Copper Interconnects Research Articles

Plasma‐Enhanced Atomic Layer Deposition of Amorphous Tantalum Thin Films for Copper Interconnects Using an Organometallic Precursor

AbstractAs integrated circuits continue to shrink in size, the demand for high‐quality adhesive layers in copper Damascene interconnects has increased. However, tantalum (Ta) films, used as liners, prepared by atomic layer deposition (ALD) from metal halide precursors, are prone to corrosion and exhibit issues such as low film density and unstable performance. In this study, Ta films are successfully fabricated using a plasma‐enhanced ALD (PEALD) process with an organometallic precursor of Ta(NtBu)(NEt2)3 (TBTDET). The study of the growth conditions reveals that introducing 10% Ar in Ar‐H2 mixed gas leads to continuous high‐quality Ta films. The deposited Ta films are free of halogen impurities, which can avoid the detrimental impact on the stability of the Cu interconnects. Although the films contain some carbon and nitrogen impurities, they do not affect the film adhesive properties. Transmission electron microscopy shows that the Ta films are amorphous, and the amorphous Ta films exhibit superior barrier properties. Moreover, highly uniform Ta films can be conformally deposited into narrow interconnect structures using this PEALD process. These findings suggest that the Ta films prepared by the organometallic precursor can offer a promising solution to address the issues related to the halogen elements in the adhesive layer preparation.

Surface Analysis of TMCTS-Based SiOC(H) Low-k Dielectrics in Post-Etch Strip of ACL Hardmask.

The miniaturization of devices requires the introduction of a high aspect ratio through patterning in the Damascene copper interconnect process. The high aspect ratio etch process employs hardmasks, such as amorphous carbon, that can withstand high-powered plasma exposure. When an etch hardmask is removed after patterning, the properties of the underlying film can be altered by the effect of plasma exposure during the strip process. In this study, surface properties of SiOC(H) are investigated after an amorphous carbon strip with O2/Ar plasma. Since the low-k film of SiOC(H) structure shows characteristics according to the Si-O internal bonding structure, the Si-O bonding ratio of the ring, network and cage structure was analyzed through Fourier-transform infrared (FT-IR) analysis to measure changes in thin film properties. X-ray photoelectron spectroscopy (XPS) was also used to add reliability to the SiOC(H) film structure. In addition, the end point of the strip process was obtained using an optical emission spectroscopy sensor and variations in thin film characteristics over the plasma exposure time were analyzed. These results revealed the structural modification of the SiCO(H) thin film in the post-etch strip of the amorphous carbon layer (ACL) hardmask.

Corrosion Protection Characteristics of Reduced Graphene Oxide Composites in Microelectronic Devices

This study investigates the effects of the corrosion protection and temperature coefficient of resistivity (TCR) properties of poly-vinyl-alcohol (PVA)/graphene oxide (GO) composites on the zinc substrate and copper (Cu) damascene interconnects. As the PVA content increased, significant amounts of fine wrinkles were observed in the films, and the coating uniformity of the composites also increased. The electrical properties of the composites indicated that the TCR can be improved by optimizing the weight % ratio of PVA/GO. After performing the accelerated corrosion test, the Cu films were lost at the coating interface and at the area without GO coating, but remained at the GO coating bottom area in the SEM and EDX observations. The results shows that corrosion of the Cu interconnects can be prevented by using the composites film and also help solve the resister–capacitor time delay problem.

Accelerating Electromigration Aging: Fast Failure Detection for Nanometer ICs

For practical testing and detection of electromigration (EM) induced failures in dual damascene copper interconnects, one critical issue is creating stressing conditions to induce the chip to fail exclusively under EM in a very short period of time so that EM sign-off and validation can be carried out efficiently. Existing acceleration techniques, which rely on increasing temperature and current densities beyond the known limits, also accelerate other reliability effects making it very difficult, if not impossible, to test EM in isolation. In this paper, we propose novel EM wear-out acceleration techniques to address the aforementioned issue. First, we show that multisegment interconnects with reservoir and sink structures can be exploited to significantly speedup the EM wear-out process. Based on this observation, we propose three strategies to accelerate EM induced failure: 1) reservoir-enhanced acceleration; 2) sink-enhanced acceleration; and 3) a hybrid method that combines both reservoir and sink structures. We then propose several configurable interconnect structures that exploit atomic reservoirs and sinks for accelerated EM testing. Such configurable interconnect structures are very flexible and can be used to achieve significant lifetime reductions at the cost of some routing resources. Using the proposed technique, EM testing can be carried out at nominal current densities, and at a much lower temperature compared to traditional testing methods. This is the most significant contribution of this paper since, to our knowledge, this is the only method that allows EM testing to be performed in a controlled environment without the risk of invoking other reliability effects that are also accelerated by elevated temperature and current density. The simulation results show that using the proposed method, we can reduce the EM lifetime of a chip from ten years down to a few hours (about 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> × acceleration) under the 150 °C temperature limit, which is sufficient for practical EM testing of typical nanometer CMOS ICs.

Fast Electromigration Stress Evolution Analysis for Interconnect Trees Using Krylov Subspace Method

Electromigration effects are a key failure mechanism for copper-based dual damascene interconnects wires in semiconductor technologies. However, accurately predicting the time-to-failure for a complicated interconnect tree in a VLSI interconnect layout requires detailed knowledge of the stress evolutions over time, and is subject to time-varying currents and temperature. This is a challenging problem as one needs to solve the stress-based partial differential equations (PDEs) in the time domain for confined copper damascene interconnect trees for both void nucleation and void growth phases. To mitigate this problem, we propose a novel Krylov subspace-based method for fast numerical solutions to the stress PDEs. The new approach, which we call FastEM , is based on the finite-difference method which is used to first discretize the PDEs into linear time-invariant ordinary differential equations (ODEs). After discretization, a modified Krylov subspace-based reduction technique is applied in the frequency domain to reduce the size of the original system matrices so that they can be efficiently simulated in the time domain. The FastEM can perform the simulation process for both void nucleation and void growth phases under piecewise constant linear current density inputs and time-varying stressing temperatures. Furthermore, we show that the steady-state response of stress diffusion equations can be obtained from the resulting ODE system in the frequency domain, which agrees with the recently proposed voltage-based EM analysis method for EM immortality checks. Numerical results show that the proposed method can lead to about 1–2 orders of magnitude speed-up over existing finite-difference time-domain-based methods on large interconnect trees for both void nucleation and growth phases with negligible errors. We further show that for most of the interconnect trees tested; we only need a small number of dominant poles for sufficient accuracy.

Sequential Lateral Solidification of Silicon Thin Films on Cu BEOL-Integrated Wafers for Monolithic 3-D Integration

We demonstrate that wafers integrated with copper (Cu) Damascene interconnects are suitable substrates for the excimer laser crystallization of silicon thin films. This approach allows for the monolithic 3-D integration of transistors on the back end of line (BEOL) of silicon wafers for VLSI monolithic 3-D integration. This is supported by a 1-D finite-element method simulation of the integrated structure, which shows that, upon excimer laser irradiation, the temperature of the buried Cu layer stays below 320 °C, which is a favorable condition for monolithic 3-D integration. The crystallization of a 100-nm amorphous silicon layer on a 1-μm SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dielectric is demonstrated on a BEOL-integrated wafer. The Raman spectrum of the silicon layer after laser irradiation shows a polycrystalline peak centered around 513 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> . Optical microscopy shows polycrystalline silicon with no physical damage of the Cu lines. The electrical characterization of the Cu buried layer, with and without undergoing the irradiation process, shows no variation or degradation in Cu conductivity.

Sequential lateral solidification of silicon thin films on low-k dielectrics for low temperature integration

We present the excimer laser crystallization of amorphous silicon on a low dielectric constant (low-k) insulator for very large scale integration monolithic 3D integration and demonstrate that low dielectric constant materials are suitable substrates for 3D integration through laser crystallization of silicon thin films. We crystallized 100 nm amorphous silicon on top of SiO2 and SiCOH (low-k) dielectrics, at different material thicknesses (1 μm, 0.75 μm, and 0.5 μm). The amorphous silicon crystallization on low-k dielectric requires 35% less laser energy than on an SiO2 dielectric. This difference is related to the thermal conductivity of the two materials, in agreement with one dimensional simulations of the crystallization process. We analyzed the morphology of the material through defect-enhanced microscopy, Raman spectroscopy, and X-ray diffraction analysis. SEM micrographs show that polycrystalline silicon is characterized by micron-long grains with an average width of 543 nm for the SiO2 sample and 570 nm for the low-k samples. Comparison of the Raman spectra does not show any major difference in film quality for the two different dielectrics, and polycrystalline silicon peaks are closely placed around 517 cm−1. From X-ray diffraction analysis, the material crystallized on SiO2 shows a preferential (111) crystal orientation. In the SiCOH case, the 111 peak strength decreases dramatically and samples do not show preferential crystal orientation. A 1D finite element method simulation of the crystallization process on a back end of line structure shows that copper (Cu) damascene interconnects reach a temperature of 70 °C or lower with a 0.5 μm dielectric layer between the Cu and the molten Si layer, a favorable condition for monolithic 3D integration.

Simulation and measurement of the capacitance benefit of air gap interconnects for advanced technology nodes

Air gap (AG) interconnects, with an ideal dielectric constant k of 1, is a promising approach to reduce signal propagation delay. In this paper, a comparative study of AG and dielectric copper damascene interconnect structures is performed through Raphael™ electric field simulation to investigate the capacitance benefit of introducing AG when scaling to small dimensions. The variation in total capacitance as a function of half pitch is simulated for different AG integration schemes proposed in the literature. Ideal and practical cases of these different integration schemes are simulated and compared to assess whether interconnect structures using a low-k (k=2.3) dielectric are more suitable than AG interconnects at scaled dimensions. The effect of using an additional (SiC-based) stiff liner on the AG capacitance benefit is also investigated. Finally, we verify our simulations using sub-40nm half pitch AG structures prepared using the conformal and non-conformal processes.

X-ray Characterization of PEALD versus PVD Tantalum Nitride Barrier Deposition and the Impact on Via Contact Resistance

Plasma enhanced atomic layer deposition (PEALD) of TaN demonstrated the significant benefit of lowering via resistance in back-end-of-line (BEOL) dual damascene copper interconnects with a line width of 32 nm, although PEALD TaN possessed a much higher intrinsic resistivity, approximately 2000 μΩcm, compared to physical vapor deposition (PVD) of Ta-rich TaN with a value around 250 μΩcm. The mechanism of lowering via resistance was studied by X-ray characterization techniques such as X-ray fluorescence (XRF) and X-ray reflectivity (XRR). XRF analysis indicated the nucleation rate of PEALD TaN is higher on a metal surface compared to a dielectric surface. XRR analysis revealed a smoother and damage free surface between PEALD TaN and silicon oxide, while a rougher interface was formed between PVD TaN and silicon oxide. Via resistance reduction with PEALD TaN is suggested to be related to reduced physical damage at the via bottom.

Fabrication and characterization of copper interconnects of line-width down to 100 nm using a specially designed phase shift mask

Resolution enhancement of traditional lithographic system is challenging. In order to improve resolution, simulation is performed and it is found that an alternating phase shift mask with alternating scatter bars provides better performance in comparison to conventional binary scatter bars. Using simulated parameters, a novel alternating phase shift mask with alternating phase shifted scatter bars is designed to fabricate damascene copper interconnects of line-width down to 100nm. Extensive characterization of the integration steps is performed for process qualification. The electrical characterization of the fabricated copper lines is also performed to assure the interconnect quality. The result of this investigation is promising and leading to an integration scheme for mass production.

Effect of downscaling nano-copper interconnects on the microstructure revealed by high resolution TEM-orientation-mapping

In this work, a recently developed electron diffraction technique called diffraction scanning transmission electron microscopy (D-STEM) is coupled with precession electron microscopy to obtain quantitative local texture information in damascene copper interconnects (1.8 µm–70 nm in width) with a spatial resolution of less than 5 nm. Misorientation and trace analysis is performed to investigate the grain boundary distribution in these lines. The results reveal strong variations in texture and grain boundary distribution of the copper lines upon downscaling. Lines of width 1.8 µm exhibit a strong 〈111〉 normal texture and comprise large micron-size grains. Upon downscaling to 180 nm, a {111}〈110〉 bi-axial texture has been observed. In contrast, narrower lines of widths 120 and 70 nm reveal sidewall growth of {111} grains and a dominant 〈110〉 normal texture. The microstructure in these lines comprises clusters of small grains separated by high angle boundaries in the vicinity of large grains. The fraction of coherent twin boundaries also reduces with decreasing line width.

Finite element simulation of hydrostatic stress in copper interconnects

This work focuses on numerical modeling of hydrostatic stress, which is critical to the formation of stress-induced voiding (SIV) in copper damascene interconnects. Using three-dimensional finite element analysis, the distribution of hydrostatic stress is examined in copper interconnects and models are based on the samples, which are fabricated in industry. In addition, hydrostatic stress is studied through the influences of different low-k dielectrics, barrier layers and line widths of copper lines, and the results indicate that hydrostatic stress is strongly dependent on these factors. Hydrostatic stress is highly non-uniform throughout the copper structure and the highest tensile hydrostatic stress exists on the top interface of all the copper lines.

Variable-shaped e-beam lithography enabling process development for future copper damascene technology

To realize fast and efficient integrated circuits the interconnect system gains an increasing importance. In particular, this is the case for logic and processor circuits with up to 12 metallization layers. In order to optimize this technology and the according processes it is desirable to generate flexible test structures in small lot production. In opposition to standard optical lithography using masks, Electron Beam Direct Write (EBDW) lithography can rapidly deliver special test structures at low cost. Furthermore, critical dimensions of future technology nodes which are not yet manufacturable by standard optical lithography tools can be produced. In this paper we demonstrate the potential of the 50kV variable shaped EBDW cluster for patterning of future back-end-of-line (BEOL) structures on full 200mm wafers. The patterned wafers have been used to develop next generation copper damascene interconnect processes for critical dimensions down to 50nm.

The effect of stress migration on electromigration in dual damascene copper interconnects

Interconnects in very large scale integration (VLSI) chips are susceptible to failure due to stress migration (SM) and electromigration (EM). At use condition, these two failure mechanisms play a collective role in causing interconnect failure. We present a study on SM and EM interaction in lower (MX structure) and upper metal (MX+1 structure) of dual-damascene Cu/low-κ interconnects. It is found that both mechanisms are dependent; statistical analysis shows that EM failure time is affected by the presence of residual stress induced by SM. This effect was more severe in the lower metal, where the EM median-time-to-failure (t50) for the majority of samples could be degraded by 30%–60%. For the upper metal of Cu interconnects, the t50 is degraded by about 10%. The reliability implication of the residual stress in copper interconnects on the EM is further investigated with various failure analysis techniques and three-dimensional finite element simulation. It is proposed that SM can influence EM when there is significant amount of vacancy accumulation due to SM in the cathode area which accelerates EM nucleation time. In the case of the MX structure, our experimental results show that SM and EM interaction occurs exactly below the via at the MX cathode side, leading to abrupt failures. On the other hand, in MX+1 structure, vacancies are likely to accumulate at the edge of upper metal lead during SM test, thus accelerating the failure during subsequent EM test. A failure mechanism model for stress evolution and void formation is proposed to provide insight into the interaction between these two failure mechanisms.

Fabrication and Characterization of Through-Substrate Interconnects

We developed a through-substrate copper-damascene interconnect technology in silicon with minimal impedance. Via impedance was extracted using parameter measurements at 50 GHz that were matched to simple circuit models. The extracted impedance shows resistances ≤ 1 Ω, record-low inductance for aspect ratios > 4, and sidewall capacitance that approaches the theoretical value. For an aspect ratio of 10 (10 in diameter and 100 high), the through-substrate via has an average inductance of 36 pH at 10 GHz, resistance of 0.6 at 1 GHz, and sidewall capacitance of 0.3 pF.

Fundamental Study of Chemical–Mechanical Polishing Slurry of Cobalt Barrier Metal for the Next-Generation Interconnect Process

A chemical–mechanical polishing (CMP) slurry was developed for use in copper (Cu) damascene interconnects with cobalt (Co) barrier metal by optimizing the corrosion potentials and removal rate selectivities of Cu and Co. A passivation layer was formed on Co surface in an alkaline solution, while no passivation layer was formed in an acidic one even with benzotriazole. In the slurry of pH 10, corrosion potential of Co was the same as that of Cu, which indicates that no galvanic corrosion between Co and Cu could occur. Furthermore, a stable Cu/Co removal rate selectivity of 0.5 was obtained with the slurry.

Helium Ion Secondary Electron Mode Microscopy For Interconnect Material Imaging

The recently developed helium ion microscope (HIM) is now capable of 0.35 nm secondary electron (SE) mode image resolution. When low-k dielectrics or copper interconnects in ultra large scale integrated circuits (ULSI) interconnect structures were imaged in this mode, it was found that unique pattern dimension and fidelity information at sub-nanometer resolution was available for the first time. This paper will discuss the helium ion microscope architecture and the SE imaging techniques that make the HIM observation method of particular value to the low-k dielectric and dual damascene copper interconnect technologies.

Electromigration in width transition copper interconnect

Electromigration (EM) experiments are conducted for submicron dual damascene copper interconnects with width transition. The direction of electron flow (from narrow-to-wide segment and wide-to-narrow segment) and the ratio of lengths (e.g. ratio of narrow-to-wide segment lengths) are found to be significant factors in determining the life-time of such interconnects. About 69% shorter EM life-time is obtained for the case of electron flow from narrow-to-wide segment, and thus to avoid over estimation of EM life-time of such interconnect system, the direction of the electron flow should be chosen appropriately in the reliability assessment. On the other hand, it is found that the width transition location is not the failure site, and finite element model is presented to explain the experimental findings.

Constraint effect in deformation of copper interconnect lines subjected to cyclic Joule heating

Temperature distributions and von Mises strains produced by cyclic Joule heating of damascene copper interconnect structures of varying geometries were calculated by finite element analysis. Constraining the top surface of the lines with rigid dielectric increased the temperature range required to produce a given strain range, relative to unconstrained lines. Much narrower lines required much higher temperatures to reach this same range of strain. Electrical tests to failure of actual structures were conducted. Scanning electron microscope images of unconstrained damascene copper lines after testing showed significant topographic features that have been associated in previous reports with mechanical fatigue. None of the constrained lines – including those cycled at ranges of total strain similar to those of the unconstrained lines – exhibited these features, but they did have large voids. Present and previously reported observations suggest that both cyclic plastic deformation and void formation can contribute to damage and failure of small-scale structures subjected to cyclic Joule heating, and that mechanical constraint has a strong effect on the operation of these mechanisms.

Evaluation of an Iron Redox-mediated Electrochemical Deposition Technique for the Damascene Copper Interconnect Process

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