Coplanar Thin-film Transistors Research Articles

Coplanar Poly-Si TFT on Flexible Metal Foil Using Spin-On Glass as Gate Insulator and Planarization

Methylsiloxane-based spin-on-glass (M-SOG) has been applied to a polycrystalline silicon thin-film transistor (TFT) on a 40 μm-thick flexible metal foil as a gate dielectric and planarization layer as well. Triple spin coatings and curing of M-SOG layers reduce the surface roughness of the metal foil from 800 to 56 A. The p-channel metal-induced crystallization of a-Si using a cap TFT using M-SOG on a metal foil exhibited a field-effect mobility of 51.1 cm 2 /V s, a threshold voltage of -4.3 V, and a minimum off-state current of <1.74 X 10 -12 A/μm at V ds = -0.1 V. The poly-Si TFT was found to be stable against a negative gate-bias stress. Therefore, the low-cost, low-temperature polycrystalline silicon TFT can be applied to make flexible displays.

A coplanar hydrogenated amorphous silicon thin-film transistor for controlling backlight brightness of liquid-crystal display

We studied a coplanar hydrogenated amorphous silicon thin-film transistor (TFT) to control the backlight brightness in liquid-crystal display (LCD). This was done by designing the inverse-staggered TFT for the switching device and the coplanar TFT to absorb the illumination from backlight. We achieved the field-effect mobility of 0.3 cm 2/V s, threshold voltage of 3.6 V, and the subthreshold voltage swing of 1.3 V/d for the coplanar TFT. The TFT showed the photocurrent of ∼10 −8 A and dark current of ∼10 −11 A in the operation region of backlight for TFT–LCD. The dynamic range was 50 dB which is good enough to control the brightness of the backlight.

A Novel Low-Temperature Polysilicon Thin-Film Transistors With a Self-Aligned Gate and Raised Source/Drain Formed by the Damascene Process

In this letter, a novel structure of the polycrystalline silicon thin-film transistors (TFTs) with a self-aligned gate and raised source/drain (RSD) formed by the damascene process has been developed and investigated. Comparing with the conventional coplanar TFT, the proposed RSD TFT has a remarkable lower off-state current (177 to 6.29 nA), and the on/off current ratio is only slightly decreased from 1.71 times 107 to 1.39 times 107. Only four photomasking steps are required. This novel structure is an excellent candidate for further high-performance large-area device applications.

Effects of the surface roughness of plastic-compatible inorganic dielectrics on polymeric thin film transistors

The effects of the roughness of the gate dielectric on the performance of thin film transistors (TFTs) fabricated with poly(2,5-bis(3-hexadecylthiophen-2-yl)thieno[3,2-b] thiophene) (PBTTT-C16) were examined. The field effect mobility of coplanar TFTs made with PBTTT-C16 and plasma-enhanced chemical vapor deposited SiO2∕SiNx dielectrics decreased nearly exponentially with surface roughness. Films of PBTTT-C16 have similar crystalline structure on smooth and rough surfaces, but the domain size decreases with increasing roughness. Surface roughness was found to have less of an impact on field effect mobility than the chemical treatment of the dielectric.

A Novel Four-Mask-Step Low-Temperature Polysilicon Thin-Film Transistor With Self-Aligned Raised Source/Drain (SARSD)

In this letter, a novel structure of polycrystalline-silicon thin-film transistors (TFTs) with self-aligned raised source/drain (SARSD) and a thin channel has been developed and investigated. In the proposed structure, a thick SD and a thin active region could be achieved with only four mask steps, which are less than that in conventional raised SD TFTs. The proposed SARSD TFT has a higher on-state current and a lower off-state leakage current. Moreover, the on/off current ratio of the proposed SARSD TFT is also higher than that of a conventional coplanar TFT

Lamination Method for the Study of Interfaces in Polymeric Thin Film Transistors

A method for the fabrication of polymeric thin-film transistors (TFTs) by lamination is described. Poly(dimethylsiloxane) stamps were used to delaminate thin films of semiconducting polymers from silicon wafers coated with a self-assembled monolayer (SAM) formed from octyltrichlorosilane. These supported films were laminated onto electrode structures to form coplanar TFTs. The fabrication process was used to make TFTs with poly(3-hexylthiophene), P3HT, and poly[5,5'-bis(3-dodecyl-2-thienyl)-2,2'-bithiophene], PQT-12. TFTs, where these polymers were laminated onto gate dielectrics coated with SAMs from octyltrichlorosilane, had effective field-effect mobilities of 0.03 and 0.005 cm2/(V s), respectively. TFTs where PQT-12 was laminated onto gate dielectrics that were not coated with a SAM also had mobility of 0.03 cm2/(V s). In contrast, TFTs fabricated by spin-coating PQT-12 onto the same structure had mobilities ranging from 10-3 to 10-4 cm2/(V s). These results suggest that the lower mobilities of polymer TFTs made with hydrophilic gate dielectrics are caused by molecular ordering in the semiconducting film rather than electronic effects of dipolar groups at the interface.

A p-channel SMC poly-Si thin film-transistor with a GOLDD structure

Abstract We have developed a silicide-mediated crystallization (SMC) polycrystalline silicon (poly-Si) thin film transistor (TFT) with a gate overlapped lightly doped drain (GOLDD) structure. Applying a GOLDD structure to the SMC poly-Si TFT, the off-state leakage current of coplanar TFT is reduced, while the reduction of the on-state current is relatively small. The p-channel poly-Si TFT with a GOLDD structure exhibited a field effect mobility of 50 cm 2 /V s and an off-state leakage current of 3.8×10 −11 A/μm at the drain voltage of −5 V and the gate voltage of 10 V.

New challenges in thin film transistor (TFT) research

This paper addresses the current trends in research and development for: (1) Thin film transistors (TFTs) on plastic substrates, (2) low-temperature poly-silicon (LTPS) for the pixel TFTs and for row and column drivers on glass, (3) addressing of organic light emitting diodes by silicon TFTs. For these advanced applications of TFTs the relevant issues are: (i) higher electron mobility, (ii) stability, and (iii) defect free, uniform deposition of thin silicon films and gate dielectrics at a high deposition rate (reduced cost). At Utrecht University, we are investigating hot wire (catalytic) chemical vapor deposition (CVD) as a deposition technique for novel TFTs that have a high potential to meet the above mentioned requirements. Bottom gate, inverted staggered TFTs with hot wire CVD (HWCVD) silicon films have been made with an electron mobility of 1.5 cm 2/ V s , and with field effect characteristics that are completely stable under operating conditions. Top gate, coplanar TFTs with polycrystalline silicon (poly-Si) films have been made, which showed a mobility of 4.7 cm 2/ V s . This has been obtained without any post treatment, and the hot wire technology can thus avoid expensive, time-consuming steps such as laser recrystallization as currently used in the production of the latest poly-Si lap top displays. HWCVD is also suitable for the deposition of SiN x :H gate dielectrics. TFTs with a hot wire silicon nitride gate dielectric have been deposited.

High Electron Mobility TFTs of Nanocrystalline Silicon Deposited at 150°oC on Plastic Foil

ABSTRACTTop gate n-channel thin film transistors (TFTs) of nanocrystalline silicon (nc-Si:H) were fabricated on Kapton polyimide film substrates at a maximum process temperature of 15°C. These are thefirst nc-Si:H TFTs ever made on a plastic substrate. Both intrinsic and n+ source/drain layers were directly deposited at 80 MHz excitation frequency for high growth rate. Coplanar TFTs with top source/drains and staggered TFTs with bottom source/drains were made. The coplanar top gate and top source/drain structures have linear electron mobility of ∼ 30 cm2V-1s-1 and ON/OFF ratio up to ∼ 105. TFTs with the top gate and bottom source/drain structure made to date have linear mobility of up to ∼ 12 cm2V-1s-1 and ON/OFF ratio of ∼105.

A polycrystalline silicon thin-film transistor with a thin amorphous buffer

We have developed a novel, low off-state leakage current polycrystalline silicon (poly-Si) thin-film transistor (TFT) by introducing a very thin hydrogenated amorphous silicon (a-Si:H) buffer on the poly-Si active layer. The a-Si:H buffer is formed on the whole poly-Si and thus no additional mask step is needed. With an a-Si:H buffer on poly-Si, the off-state leakage current of a coplanar TFT is remarkably reduced, while the reduction of the on-state current is relatively small. The poly-Si TFT with an a-Si:H buffer exhibited a field effect mobility of 12 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs and an off-state leakage current of 3 fA/μm at the drain voltage of 1 V and the gate voltage of -5 V.

Low-temperature polysilicon thin-film transistors fabricated from laser-processed sputtered-silicon films

In an effort to develop a simple low-temperature high-performance polysilicon thin-film transistor (TFT) technology, we report a fabrication process featuring laser-crystallized sputtered-silicon films. This top Al-gate coplanar TFT process subjects the substrate to a maximum temperature of 300/spl deg/C, and produces devices with mobilities up to 450 cm/sup 2//Vs, on/off current ratios greater than 10/sup 7/, without using a post-hydrogenation step. We believe these results represent the highest performance TFT's to date fabricated from sputtered silicon films.

High-Mobility Thin-Film Transistor Fabricated Using Hydrogenated Amorphous Silicon Deposited by Discharge of Disilane

Plasma-enhanced chemical vapor deposition of hydrogenated amorphous silicon (a-Si:H) film was investigated with emphasis on the effect of disilane flow rate. A coplanar thin-film transistor (TFT) was fabricated using this a-Si:H film. Silicon-hydrogen bond content in the a-Si:H film was measured by infrared absorption spectroscopy. With decrease in the disilane flow rate from 3.0 cm3/min to 1.5 cm3/min, the maximum field-effect electron mobility (µ FE) of the TFT which depends on the gate voltage increased from 3.3 cm2/( V·s) to 4.9 cm2/( V·s), accompanied by a reduction in the silicon-hydrogen bond content. There was a negative correlation between µ FE and the silicon-hydrogen bond content in the a-Si:H film. The improvement mechanism of µ FE was discussed in terms of the chemical structure of the a-Si:H film.

Tetrahedrally bonded amorphous carbon (ta-C) thin film transistors

The authors describe a glass compatible, carbon-based, metal-insulator- semiconductor field effect transistor (MISFET). Tetrahedral amorphous carbon (ta-C) is used, for the first time, as the active semiconductor layer in a coplanar thin film transistor (TFT) structure.

High‐performance polycrystalline silicon tfts using self‐aligned grain boundary control technique

AbstractTo improve the reproducibility of the properties of thin‐film transistors (TFTs) formed by using solid‐phase grown polycrystalline silicon, a self‐aligned grain boundary control technique was developed. In this technique, the gate electrode of a coplanar TFT serves as a mark for ion implantation to the source and drain regions. At the same time, it limits amorphization of polycrystalline silicon only to the channel region. The channel region becomes amorphized by a high‐energy silicon ion beam through the gate electrode and oxide. However, since the silicon ions penetrate through the source and drain regions, crystalline seeds remain in the regions. Then the solid‐phase growth is carried out in the regions from the source and drain regions to the center of the channel before the crystalline nuclei are formed in the channel region.By this process, the presence of the grain boundary is limited to the center of the channel. When this technique is used, the mobility is improved by 60 percent and the scattering of the mobility value is reduced to half.

Ion-Beam Deposition of Thin Films of Diamondlike Carbon

An ion-beam deposition technique has been developed and was used to deposit thin films of insulating carbon on room-temperature substrates. It was established that the carbon films deposited using this technique are insulating and have the following characteristics similar to that of carbon in the diamond form: (1) transparency, (2) index of refraction greater than 2.0, (3) highly insulating, (4) able to scratch glass, (5) resistant to hydrofluoric acid for long periods of time, (6) at least partially crystalline and with a lattice constant similar to diamond as demonstrated by x-ray diffraction, (7) dielectric constant between about 8 and 14 (diamond is 16.5). A resistance to sodium ion diffusion has been experimentally demonstrated. Preliminary measurements at a dose of 1 Mrad indicated a radiation resistance from the point of view of stability of leakage resistance and of negligibly small flat band voltage shifts. Several coplanar thin-film transistors using the insulating carbon gate have been fabricated.