Lamination Method for the Study of Interfaces in Polymeric Thin Film Transistors

Abstract

A method for the fabrication of polymeric thin-film transistors (TFTs) by lamination is described. Poly(dimethylsiloxane) stamps were used to delaminate thin films of semiconducting polymers from silicon wafers coated with a self-assembled monolayer (SAM) formed from octyltrichlorosilane. These supported films were laminated onto electrode structures to form coplanar TFTs. The fabrication process was used to make TFTs with poly(3-hexylthiophene), P3HT, and poly[5,5'-bis(3-dodecyl-2-thienyl)-2,2'-bithiophene], PQT-12. TFTs, where these polymers were laminated onto gate dielectrics coated with SAMs from octyltrichlorosilane, had effective field-effect mobilities of 0.03 and 0.005 cm2/(V s), respectively. TFTs where PQT-12 was laminated onto gate dielectrics that were not coated with a SAM also had mobility of 0.03 cm2/(V s). In contrast, TFTs fabricated by spin-coating PQT-12 onto the same structure had mobilities ranging from 10-3 to 10-4 cm2/(V s). These results suggest that the lower mobilities of polymer TFTs made with hydrophilic gate dielectrics are caused by molecular ordering in the semiconducting film rather than electronic effects of dipolar groups at the interface.