Conventional Si Process Research Articles

Triaxial tactile sensor utilizing standing laser-induced graphene cantilevers on polyimide film

Microelectromechanical systems (MEMS) multiaxial tactile sensors have been developed in various fields to leverage their small size, high accuracy, and high sensitivity. Although various measurement principles have been proposed, most tactile sensors are fabricated using conventional and complicated Si processes. Conversely, laser-induced graphene (LIG) has recently attracted significant attention as a material for fabricating physical sensors due to its high sensitivity as a piezoresistor through simple laser processing. Therefore, the application of LIG to MEMS processes is expected to yield unprecedented MEMS sensor devices. In this paper, we propose a triaxial tactile sensor using standing LIG cantilevers embedded in an elastic body. The proposed sensing element was fabricated using ultraviolet (UV) laser irradiation to shape a polyimide film into cantilever structures and CO2 laser irradiation to form LIG strain gauges. Subsequently, the flat LIG cantilevers were stood up using thermal deformation. These multiple three-dimensional LIG cantilever elements enable multiaxial force measurements. The cantilever and elastic body portion of the sensor had dimensions of 3 × 3 × 0.2 mm and 12.5 × 12.5 × 3 mm, respectively. The fabricated sensor response was evaluated, and its capability to independently measure triaxial forces was verified. Therefore, the proposed simple and reproducible fabrication process is useful for realizing compact multiaxial tactile sensors.

(Invited) Polycrystalline Ge-Based Thin Films with High Carrier Mobility

Low-temperature synthesis of high-performance semiconductor thin films on insulators is a key technology to integrate functional devices into Si-LSIs, flat panel displays, and various sensors surrounding us. Ge and Ge-based semiconductors, such as SiGe and GeSn, have higher carrier mobility and lower crystallization temperature than Si, in addition to good compatibility with conventional Si process. In recent years, Ge-MOSFET mobilities have exceeded those of Si-MOSFETs because of the development of device technologies including gate stacks. Conversely, a thin film structure is preferable to a bulk structure to suppress leakage current derived from the narrow band gap. For these reasons, Ge-based thin films are very promising as a channel material for advanced thin film transistors (TFTs). However, the performance of Ge-TFTs is currently limited by the crystallinity of the Ge thin film itself. To improve the device performance, it is essential to innovate the synthesis technology of Ge thin films on insulators.Generally, a polycrystalline Ge (poly-Ge) layer has a high hole concentration because of defect-induced acceptors and a low carrier mobility due to grain boundary scattering.1 In low-temperature (< 500 °C) solid-phase crystallization (SPC) process, we found that the densification of the amorphous Ge (a-Ge) precursor significantly enlarged the grain size and reduced the grain boundary barrier height of the resulting poly-Ge.2 Based on the finding, we have continuously updated the Hall hole mobility of Ge layers formed on insulators (Fig. 1 (a)).3,4 It is attractive that the hole mobility exceeds that of a single-crystal Si wafer, even though the Ge layers are polycrystalline formed by a simple process. The TFT based on the Ge layer exhibited the highest performance among low-temperature Ge-TFTs.5 Because the densified a-Ge crystallizes even at < 400 °C, a flexible plastic can be used for the substrate.4 An n-type poly-Ge layer with a high electron mobility is also achieved by SPC of a-Ge containing n-type dopants (Fig. 1(b)).6,7 Further, we have demonstrated that the advanced SPC technique is useful for SiGe8 and GeSn9,10 alloys. This technique may be universally applicable to other materials, and is currently being applied to III-V compound semiconductors.In this talk, I will discuss (i) the effects of density modulation and doping in Ge precursors on subsequent SPC and (ii) the composition effects of SiGe and GeSn alloys on the growth and electrical properties.[1] K. Toko et al., Solid State Electronics 53, 1159 (2009).[2] K. Toko et al., Sci. Rep. 7, 16981 (2017).[3] R. Yoshimine et al., Appl. Phys. Express 11, 031302 (2018).[4] T. Imajo et al., Appl. Phys. Express 12, 015508 (2019).[5] K. Moto et al., Appl. Phys. Lett. 114, 212107 (2019).[6] D. Takahara et al., Appl. Phys. Lett. 114, 082105 (2019).[7] M. Saito et al., Sci. Rep. 9, 16558 (2019).[8] D. Takahara et al., J. Alloys Compd. 766, 417 (2018).[9] K. Moto et al., Sci. Rep. 8, 14832 (2018).[10] K. Moto et al., Appl. Phys. Lett. 114, 112110 (2019). Figure 1

Degradation of 4H-SiC IGBT threshold characteristics due to SiC/SiO2 interface defects

Previously reported measurements of the interface state density at the 4H-SiC/SiO2 interface and carrier recombination in the SiC substrate are incorporated into the device simulation of a 4H-SiC IGBT trench-type device structure. Cross-sectional simulation results show two important degradation characteristics on the conduction current; shift of the threshold voltage toward higher gate voltages due to the deep traps and reduction of the current magnitude due to the shallow traps. The wide bandgap of SiC and the high interface defect density magnitude distributed widely within the bandgap due to conventional SiC/SiO2 process technology make SiC-based devices prone to degradation, which are observed not only as a subthreshold-slope degradation but also causes variations of the threshold voltage. Conventional Si process technology usually results in a dominating homogeneous shallow-type trap which only results in a degradation of the subthreshold-slope.

Scanning probe study on the photovoltaic characteristics of a Si solar cell by using Kelvin force microscopy and photoconductive atomic force microscopy

Poly-Si-based solar cells, prepared via conventional Si processes including phosphoryl chloride(POCl3) doping and diffusion, were investigated in this study in terms of their electrical and optical properties, including open-circuit voltage (Voc), short-circuit current (Isc), fill factor, external quantum efficiency and efficiency, employing a few recognized test methods. Also, we compared the experiment results from an identical specimen via Kelvin force microscopy (KFM) and photoconductive atomic force microscopy (PC-AFM), respectively, verifying that the scanning probe technique is very effective both in photovoltaic effect measurement and mechanism establishment. When the results of both conventional and nano-probing techniques are compared, the behavior of the surface potential property is similar to the Voc, and that of the photoinduced current property is similar to the Isc. Through this study, we have demonstrated that the KFM and the PC-AFM are effective tools to monitor and evaluate the properties of solar energy–producing materials and devices.

Study on the correlation between the photovoltaic effect and the defect density at the surface of a poly-Si solar cell by using photoconductive atomic force microscopy (PC-AFM)

In this study, we designed and fabricated a poly-Si-based solar cell device by using conventional Si processes. The electrical properties, such as the open-circuit voltage (Voc), the short-circuit current (Isc), the fill factor, the external quantum efficiency (EQE) and the efficiency of prepared solar cell devices, were characterized with a standardized measurement system. Also, the correlation between the photoinduced current and the variation of the defect density was then investigated for various locations by using a photoconductive atomic force microscopy (PC-AFM) system. We verified that in a high-defect-density region such as a grain boundary, a triple junction or a crack, photoinduced carriers easily recombined and induced a decrease in the diffusion length and a low level of photoinduced current. Moreover, we suggest a very effective method to reduce the contact resistance between the cantilever tip and the sample surface, which can disturb the flow of photoinduced current.

Compressive Uniaxial Stress Bandstructure Engineering for Transferred-Hole Devices

The transport properties of holes in Si, Ge, and Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Ge under high compressive stresses are studied with a Monte Carlo simulation method. Stress significantly improves the low-energy mass and mobility, while its effect is diminished in the high-energy bandstructure. The transient behavior of the carrier velocity exhibits a double-overshoot peak at high driving field. This double-overshoot behavior is manifested in carrier-velocity profiles in simulated short-channel PMOS devices. In steady state at lower field, the hole velocity exceeds the saturation velocity at high field. This leads to a negative differential resistance effect in simulated resistors. We propose to use this effect, generic to cubic semiconductors, for transferred-hole devices. An advantage of this approach is that it can be integrated into the conventional stress-engineered Si or Ge logic process.

Electrical Characteristics of Hybrid Nanoparticle–Nanowire Devices

Gold nanoparticles synthesized by a colloidal method were deposited in an Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> dielectric layer of an omega-gated single ZnO nanowire FET. These gold nanoparticles were utilized as localized trap sites. The adsorption of the gold nanoparticles on an Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> -coated ZnO nanowire was confirmed by high-resolution transmission electron microscopy. In this study, a hybrid nanoparticle-nanowire device was fabricated by conventional Si processing. Its electrical characteristics indicated that electrons in the conduction band of the ZnO nanowire can be transported to the localized trap sites by gold nanoparticles for gate voltages greater than 1 V, through the 10-nm-thick Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> tunneling oxide layer.

A Layered Finite Element Method for Electromagnetic Analysis of Large-Scale High-Frequency Integrated Circuits

A high-capacity electromagnetic solution, layered finite element method, is proposed for high-frequency modeling of large-scale three-dimensional on-chip circuits. In this method, first, the matrix system of the original 3-D problem is reduced to that of 2-D layers. Second, the matrix system of 2-D layers is further reduced to that of a single layer. Third, an algorithm of logarithmic complexity is proposed to further speed up the analysis. In addition, an excitation and extraction technique is developed to limit the field unknowns needed for the final circuit extraction to a single layer only, as well as keep the right-hand side intact during the matrix reduction process. The entire procedure is numerically rigorous without making any theoretical approximation. The computational complexity only involves solving a single layer irrespective of the original problem size. Hence, the proposed method is equipped with a high capacity to solve large-scale IC problems. The proposed method was used to simulate a set of large-scale interconnect structures that were fabricated on a test chip using conventional Si processing techniques. Excellent agreement with the measured data has been observed from dc to 50 GHz

P-4: Microcrystalline Silicon TFTs for Active Matrix Displays

Microcrystalline silicone (μ-Si:H) TFTs were fabricated using a conventional bottom gate amorphous Si (a-Si:H) process. A unique μc-Si:H deposition technique and TFT architecture was proposed to enhance the reliability of the TFTs. This three-mask TFT fabrication process is comparable with existing a-Si:H TFT process. In order to suppress nucleation at the bottom interface, a N2 plasma passivation was conducted before the deposition of the μc-Si:H. A typical transfer characteristic of the TFTs shows a low off-current with a value of less than 1 pA and a sub-threshold slope of 0.7 V/dec. DC bias stress was applied to verify the use of μc-Si:H TFTs for AMOLED displays. After 10,000 s of stress application time, the off-current was even lowered and sub-threshold slope variation was less than 5%. For AMOLED displays, OLED pixel simulation was performed. A pixel current of 13 μA was achieved with a Vdata of 10 V. After the simulation, a linear equation for the pixel current was derived. We also present the simulation tests of simple logical electronics. At last, for Active matrix Display back-plane, a row driver with no shift compensation is simulated with good results in terms of reproducibility and reliability.

Growth of (001) oriented La0.5Sr0.5CoO3 films directly on SiO2/Si substrate by pulsed laser deposition

Growth and structural evolution of La0.5Sr0.5CoO3 thin films fabricated directly on SiO2/Si substrate by pulsed laser deposition were investigated. Films deposited at 780 °C and oxygen partial pressure of 2 Pa showed highly c-axis orientation. Films with low electrical resistivity of 2×10−3 Ω cm were obtained by annealing at 650 °C for 40 min. C-axis oriented Ba0.5Sr0.5TiO3 thin film was then grown on the La0.5Sr0.5CoO3 film, and large dielectric tuning (>50%) was achieved. This method may have good prospect for the integration of ferroelectric materials with conventional Si process technology.

Tensile strained Ge p-i-n photodetectors on Si platform for C and L band telecommunications

We demonstrate a 0.25% tensile strained Ge p-i-n photodetector on Si platform that effectively covers both C and L bands in telecommunications. The direct band edge of the Ge film has been pushed from 1550 to 1623 nm with 0.25% tensile strain, enabling effective photon detection in the whole L band. The responsivities of the device at 1310, 1550, and 1620 nm are 600, 520, and 100mA∕W under 0 V bias, which can be further improved to 980, 810, and 150mA∕W with antireflection coating based on calculations. Therefore, the device covers the whole wavelength range used in telecommunications. The responsivities at 1310 and 1550 nm are comparable to InGaAs photodetectors currently used in telecommunications. In the spectrum range of 1300–1650 nm, maximum responsivity was already achieved at 0 V bias because carrier transit time is much shorter than carrier recombination life time, leading to ∼100% collection efficiency even at 0 V bias. This is a desirable feature for low voltage operation. The absorption coefficients of 0.25% tensile strained Ge in the L band have been derived to be nearly an order of magnitude higher than bulk Ge. The presented device is compatible with conventional Si processing, which enables monolithic integration with Si circuitry.

All Si-based optical interconnect for interchip signal transmission

Barriers to the commercial implementation of optical interconnects between integrated circuits (ICs) center around the fabrication of optical elements on wafers through conventional Si processes. Most other approaches for optical interconnects use direct bandgap emitters that require drastic changes in conventional fabrication processes. In this work, we demonstrate the ability to transmit electrical signals using Si-based components, i.e., the light was generated by biasing a p-n junction at avalanche breakdown voltage, light was coupled through a fiber cable made of SiO/sub 2/, and detected by an Si-based avalanche photodiode. Results presented demonstrate the switching behavior of the light emitter, transmission of the signal across the fiber, and measurement of the signal limited by the bandwidth of the receiver amplifier.

Structure and Properties of Quasi-Monocrystalline Silicon Thin-Films

ABSTRACTThis contribution describes the preparation of a single crystalline Si thin-film separable from a reusable Si wafer. The method relies on: i) etching of a porous silicon layer ii) high-temperature annealing and iii) transfer of the recrystallized film to a foreign substrate. As a result of the process we obtain 1 to 30 μm thick monocrystalline Si films that contain voids with a size of several 100 nm. Due to its “swiss-cheese-like” structure the material is termed as “quasi-monocrystalline Si”. Sub micrometer thin layers are almost compact, while in several micron thick films voids cause scattering of incident light. This effect increases the effective absorption coefficient by light trapping and seems promising for the application of our quasi-monocrystalline films in thin film solar cells. Quasi-monocrystalline p-type silicon reaches a hole mobility of 78 cm2/ Vs measured by room-temperature Hall-effect. High carrier mobility and adjustable optical characteristics make these films suitable for display and photovoltaic applications. Quasi-monocrystalline films are processed using conventional high-temperature Si processing; finished devices can be transferred to a foreign substrate such as glass, while the starting wafer can be reused several times.

Fabrication and performance characteristics of high-speed ion-implanted Si metal–semiconductor–metal photodetectors

We have fabricated high-speed Si metal-semiconductor-metal photodetectors using(19) F(+) ion implantation in low-doped Si. Bandwidths in excess of 6 GHz have been obtained that represent more than an order-of-magnitude improvement over unimplanted counterparts. Measurements with short optical pulses show that the increase in bandwidth is due primarily to a shorter carrier lifetime in implanted devices. In the absence of implantation, the response under short optical pulse excitation has a long decay with a time constant of ~0.35 ns. We carried out an optical fiber transmission experiment using a GaAs (lambda ~ 0.85 mum) laser source and the implanted Si photodetector. Error-free transmission (bit error rate < 10(-11)) with good receiver sensitivity was obtained at 2 Gbits/s. These results demonstrate that implanted Si can be used as a detector for short-wavelength fiber-optic communication systems for speeds to a few gigabits per second. Monolithic integration of this detector technology with conventional Si processing offers the potential for low-cost receiver designs.

Electrical Properties of Schottky Contacts of TiW on RTCVD Si1-x-yGexCy Films

ABSTRACTHigh-quality epitaxial Si1-x-yGexCy layers were grown on Si by rapid thermal chemical vapor deposition. Schottky diodes of TiW/SiGeC were fabricated using conventional Si processes. I-V and C-V measurements were performed to assess effects of crystal defects in the alloy on the electrical properties. For defective SiGeC films due to non-substitutional carbon, high series resistance and additional tunneling current were measured under forward bias, as well as leakage current under reverse bias. A transport mechanism of deep generation/recombination centers formed by carbon complexes is proposed to explain the I-V characteristics.

Step arrangement design and nanostructure self-organization on Si(111) surfaces by patterning-assisted control

We propose a new approach to self-organize atomic step arrangement on Si(111) surfaces on a wafer scale. Steps originating in substrate misorientation are rearranged on surfaces patterned with small hole arrays during high temperature annealing in an ultra high vacuum. After further annealing, the holes are completely filled, and only ordered step bands are left on the surface. Inside the unfilled holes appear trimmed nanostructures, reflecting the dependence of step behaviors on the misorientation direction. The present technique is promising for large scale control of step-initiated nanofabrication as well as for improving the conventional Si process in which an atomically flat surface is increasingly required.

High-Mobility p-Channel Metal-Oxide-Semiconductor Field-Effect-Transistor on Strained Si

An enhancement-mode high-mobility p-channel metal-oxide-semiconductor field-effect-transistor (MOSFET) is fabricated on strained Si layer for the first time. A biaxially strained thin Si layer is pseudomorphically grown on a relaxed GeSi buffer on Si substrate by molecular beam epitaxy (MBE). MOSFETs are fabricated using conventional Si process technology. It is found that low-field channel mobility of PMOSFET on strained Si is 50% higher than that of PMOSFET on bulk Si.

Excimer laser planarization of AlSi, AlSiTi and AlSiCu alloys

In this work we use a XeCl excimer laser (λ = 308 nm) to planarize three Al alloys, namely AlSi(1%), and AlSi(1%)Ti(0.1%), and AlSi(1%)Cu(0.5%). AlSi(1%) is currently the dominant first level metalization used in production because of its low resistance and compatibility with conventional Si processes. The Ti and Cu are added to suppress hillocking and improve electromigration resistance. Our results show that excellent planarization is achieved for all topologies including submicron contact hole structures, however, for the AlSi alloy spot ablation occurs which is characterized by the removal of metal. This is not seen for the AlSiCu and the AlSiTi alloys. The best morphology is obtained for the AlSiTi alloy with large areas completely free of ablation and pitting, which indicates that excellent planarization over large device areas can be achieved using this alloy.

Low loss Si_3N_4–SiO_2 optical waveguides on Si

We have developed an optical integrated circuit waveguide technology based on conventional Si processing. We demonstrate waveguide losses of <0.3 dB/cm in the 1.3-1.6-microm wavelength range. We use a high refractive-index core of Si(3)N(4) surrounded by SiO(2) cladding layers, which provides a highly confined optical mode adequate for butt coupling to channel substrate buried heterostructure lasers. We report the first IR transmission experiments in these waveguides and find two absorption peaks associated with H in SiO(2) and Si(3)N(4) layers at 1.40 and 1.52 microm, respectively. The peak absorptions are 2.2 and 1.2 dB/cm, respectively, and these peaks can be largely removed by annealing at 1100-1200 degrees C.

TV Tuners Using Low Loss and Low Distortion GaAs Varactor Diodes

The noise figure of conventional TV varactor tuners is fairly high, when typical Si diodes, whose average resistance is 0.65?at 470 MHz, are used. Low noise tuners which comply with FCC noise requirements can be realized if low loss varactor diodes are developed. However, Si diodes with still lower losses can not be manufactured by conventional Si process technology with high production yield. Low noise Si rf transistors with a noise figure of 1.3 dB at 470 MHz is commercially available. However, noise figure improvement using these transistors at 470 MHz is only 1.0 ~ 1.2 dB when compared with conventional tuners. These low noise Si transistors are high in cost and low in production yield because the specification uniformities are insufficient.