Conventional Shallow Trench Isolation Research Articles

Adjustable Silicon Corner Rounding Radius by Wet Technique

Shallow trench isolation (STI) and active area (AA) top corner rounding is important to devices performance. AA top corner rounding techniques include STI etch, linear oxidation , H2 annealing and wet oxide pull back (PB). However, conventional STI etch will caused AA facet and need to additional thermal in linear oxidation or H2 annealing processes. Wet oxide PB is easily to control the pad oxide etching amount and reach desired AA top corner top rounding radius.In this study, different pad oxide PB amount by Hydrogen Fluoride (HF) with corner rounding correlation were shown. At high pad oxide PB amount, additional hydrogen peroxide (H2O2) with dilute HF can optimize the AA top corner profile and enlarge the corner radius. Sharp AA corners profile caused gate oxide formation thickness thinning let strong electrical filed at AA corner. In wafer acceptable test had brought about double hump effect in I-V characteristics and inverse narrow width effect. Pad oxide PB following STI Etch is used by HF to let the silicon top corner be exposed and beneficial for increasing AA top corner rounding radius of liner oxidation process. This study gives some course to improve the silicon corner profile and AA top corner radius. After STI etch process, different wet etch amount were used for pad oxide PB from pad nitride by 0.49% HF process time adjustment. Different wet oxide PB amount were split for corner radius comparison. As oxide PB amount increased from 0nm to 5nm the corner radius can be improved, and the best radius showed at PB 5nm. When oxide PB amount add to 7.5nm, the corner radius became worse slightly. The radius of PB 10nm is even worse and close to without oxide PB process. This result suspected that AA corner profile might be changed in wet oxide PB process. When oxide PB amount increase, oxide etch rate might decrease and exposed silicon corner be continually damaged by HF erosion. The silicon damage of PB 5nm is slight and can be recovered after linear oxidation thermal process. At PB 7.5nm the AA corner “stepped” profile was observed. It can explain while the PB amount >5nm the corner rounding radius decrease. Because the “stepped” profile caused the corner split two curvatures then the radius decrease. The “stepped” profile of PB amount >7.5nm still be find after linear oxidation. To reduce the AA top corner “stepped” profile, the post-HF treatment’s AA silicon exposed in following APM process. The AA top corner and silicon sidewall which with APM treatment is clipping suspect H2O2 oxidize silicon and NH4OH consume the oxide caused. This profile made the region of exposed silicon to be deficient and pointed in AA geometry of silicon corner. The pointed AA top corner profile is unhelpful for corner rounding radius improvement, so the key factor of AA top rounding profile is corner silicon loss controller. In order to reduce the corner silicon loss amount, using H2O2 to replace the APM and dilute HF concentration to do oxide PB. This optimistic experience will be expected lower the exposed corner silicon consumption and corner rounding radius improvement. According oxide PB amount 5nm and 7.5nm comparison in 0.49%HF, the corner radius reduced 0.1nm when the PB increased. Nonetheless, HF concentration changed from 0.49% to 0.1% and H2O2 addition, the corner radius can be improved 0.3nm and 0.7nm. This result proved that the corner silicon profile of PB >5nm will be damaged in concentrated HF wet etch. Change to dilute HF concentration will reduce corner silicon loss and enable to recover corner silicon which with “stepped” profile by additional H2O2 treatment. As the higher oxide PB amount the pad oxide PB rate will become lower cause that without oxide protected corner silicon will be damaged and result in “stepped” profile. Nevertheless, using dilute HF can lower corner silicon loss and reduce the silicon erosion which without oxide protected. Additional H2O2 treatment introduced the rounding and smooth profile. The relationship between pad oxide PB and AA top corner rounding is established in STI process. The AA top corner radius of oxide PB amount 5nm can be improved 2.6nm compare to without PB process. When oxide PB amount >5nm the corner radius is decreased. The decreasing corner radius come from higher oxide PB amount that without oxide protected corner silicon will be damaged. This phenomenon result in “stepped” profile with difference curvature and corner radius decreasing. Dilute HF with H2O2 treatment is demonstrated that it is beneficial to reduce and recover the corner damaged. Figure 1

Adjustable Silicon Corner Rounding Radius by Wet Technique

Shallow trench isolation (STI) and active area (AA) top cornerrounding is important to device performance. AA top cornerrounding techniques include STI etch [1], linear oxidation [2], H2annealing [3] and wet oxide pull back (PB). However,conventional STI etch will caused AA facet and needs additionalthermal in liner oxidation or H2 annealing processes. Wet oxide PBeasily controls the pad oxide etching amount and reaches thedesired AA top corner top rounding radius. In this study, differentpad oxide PB was achieved by hydrogen fluoride (HF) etching andcorrelated with corner rounding. For high pad oxide PB, additionalhydrogen peroxide (H2O2) with dilute HF (DHF) can optimize theAA top corner profile and enlarge the corner radius.

A New On-Chip ESD Strategy Using TFETs-TCAD Based Device and Network Simulations

For the first time, this paper reports the quasi-static behavior and the applicability of the tunnel field effect transistor (TFET) for the on-chip electrostatic discharge (ESD) protection. ESD evaluations are performed on 28-nm fully depleted silicon-on-insulator (FDSOI), bulk TFET and compared with conventional shallow trench isolation (STI) diode using a well calibrated 3-D technology computer aided design (TCAD) device and process simulation deck. Initial design insights are obtained using the DC characteristics. The quasi-static behavior of a TFET is studied by applying transmission line pulsing (TLP) and very fast TLP (VFTLP) pulses at its drain terminal with gate shorted together and source connected to the ground. During negative TLP pulse at the drain, the TFET becomes a forward biased gated diode and exhibits reduced on-resistance compared to the STI diode. During positive TLP pulse, the tunneling current at the source-channel junction introduces a low impedance current path from drain to source compared to the blocking behavior of the STI diode. A short description of the advantages and challenges of the TFET from ESD perspective are also discussed. Finally, a new TFET ESD network is proposed and shown to exhibit multiple current paths compared to STI diode-based ESD network. From the network simulations, the proposed TFET-based ESD network is shown to exhibit better CDM response and hence providing a robust ESD solution for future system-on-chip design.

Innovative Gap-Fill Strategy for 28 nm Shallow Trench Isolation

At the 28 nm technology node, the conventional Shallow Trench Isolation (STI) gap-fill process shows some filling limitations due to voids formation in the oxide layer (SiO2), leading to electrical isolation trouble. In this paper, a new gap-fill strategy called L-E-G (for Liner - Etch-back - Gap-fill) is presented. This strategy is based on an innovative etch-back step, using downstream plasma, which allows liner profile reshaping and improves the slope in trenches. First, the etch-back process on blanket wafers is studied. A slowdown phenomenon of the etch rate with plasma exposure time is observed. Then, the relation between plasma conditions and liner profile reshaping is established. Finally, the L-E-G strategy is applied on 28 nm technology wafers. Successful STI void-free is obtained.

Terahertz Schottky barrier diodes with various isolation designs for advanced radio frequency applications

High performance nanometer NiSi2-Si Schottky barrier diode arrays (SBDA) with various isolation designs, including poly Si gate (PSG) and resist protection oxide (RPO), are developed for advanced radio frequency applications. Radio frequency performances of these developed SBDAs are investigated and compared to that with the conventional shallow trench isolation. All of the SBDAs are fabricated with a foundry state-of-the -art 45 nm complementary metal oxide semiconductor technology. Both of PSG and RPO insulated SBDAs have higher cutoff frequency and a simpler preparation process. Specifically, the PSG insulted SBDA could achieve a cutoff frequency of up to 4.6 THz.

Dry etching process for bulk finFET manufacturing

This paper describes a method to manufacture bulk fins for finFET. The bulk fins consist of two parts: the straight top of 125 nm height which is used as a fin and a sloped bottom of 200 nm one that facilitates the trench filling. The method is based on a conventional shallow trench isolation (STI) process flow with an additional α-C hard mask of 90 nm (with antireflective SiOC coating of 35 nm) on top of the STI stack (70 nm nitride on top of 8 nm oxide). The nitride layer and the top straight part of the fin is patterned using CH 2F 2/SF 6/N 2 chemistry and α-C as a mask, while the bottom sloped part is patterned using Cl 2/O 2/N 2 chemistry and the nitride layer as a mask. After the etching, the STI process flow remains almost unchanged.

Reduction of oxide leakage currents of EEPROM at STI corners using sacrificial oxide/liner SiN/LPCVD MTO

Shallow trench isolation (STI) is the predominating isolation technology for advanced integrated circuits, but the oxide thickness of the convex corner of trenched Si surfaces is thinner than other planar Si surfaces, which causes leakage currents and gate oxide reliability degradation of electrically erasable and programmable read only memory (EEPROM) by the keen convex corner region. We present an improved shallow trench isolation process to reduce leakage currents by sacrificial thermal oxide, liner silicon nitride, and Low Pressure Chemical Vapor Deposition Medium Temperature Oxide (LPCVD MTO). We found that the sample fabricated by an improved STI process with sacrificial oxidation of EEPROM decreased leakage currents and eliminated humps shown at the samples fabricated by conventional STI process, and also obtained more improved endurance characteristics stress biases applied at wordlines. In spite of the shortcoming that it provides a few additional shallow trench isolation process steps, it is an effective method to reduce oxide leakage currents and alleviate oxide reliability degradation.

Thick-Strained-Si/SiGe CMOS Technology With Selective-Epitaxial-Si Shallow-Trench Isolation

We developed a new bulk strained Si/SiGe CMOS technology free from any Ge-related problems, which has a 90- to 110-nm strained Si layer thicker than the limit at which misfit dislocations occur and a new shallow-trench isolation (STI) structure that has a selective-epitaxial-Si (SES) layer to cover up the SiGe trench surface. This technology has advantages in process compatibility with Si CMOS because it allows rough treatment of cap Si surface cleaning or sacrificial oxidation. The thick-strained Si exactly causes misfit dislocations at the interface of Si/SiGe, but no degradation of the internal strain was observed. The dislocation depth is deep enough to reduce the leakage current between source and drain. SES-STI has advantages in low junction leakage current and manufacturing compatibility with Si-CMOS process. The fabricated thick-strained-Si/SiGe 0.18-mum CMOS shows the same performance enhancement factor as the usual thin (< 20 nm) strained Si/SiGe. SES-STI reduced the junction leakage current by 1.5-2 decades from the conventional STI without epitaxial Si layer. Hot carrier lifetime is the same or rather longer than control Si, which means that the quality of the gate oxide on thick-strained Si is not inferior to that of control Si.

Elevated field insulator (ELFIN) process for device isolation of ultrathin SOI MOSFETs with top silicon film less than 20 nm

New device isolation process, called elevated field insulator (ELFIN) process, for ultrathin SOI devices with top silicon film less than 20 nm has been proposed and successfully demonstrated. In ELFIN process, gate oxidation and subsequent gate poly-Si deposition is followed by conventional STI process. ELFIN process has a field region elevated compared with active silicon region, leading to prevention of silicon edge from being wrapped around by gate poly-Si. It is found that thin-film SOI NMOSFETs with ELFIN process have better reverse narrow channel effect about 50% at W/sub G/=0.3 /spl mu/m than that with conventional shallow trench isolation (STI) process.

Process Design for Preventing the Gate Oxide Thinning in the Integration of Dual Gate Oxide Transistor

In this study, a method is proposed to alleviate a gate oxide (GOX) thinning problem at the edge of shallow trench isolation (STI), when STI is adopted in the dual gate oxide process (DGOX). It is well known that the DGOX process is usually used for realizing both low and high voltage operating parts in one chip. However, it is found that severe GOX thinning occurs from 320 Å (in active area) to 79 Å (at STI top edge) and a dent profile exists at the top edge of STI, when conventional DGOX and STI processes are adopted. In order to solve these problems, a new DGOX process is used in this study. The GOX thinning is prevented mainly by a combination of a thick sidewall oxide with SiN pullback. Therefore, good subthreshold characteristics without a so-called double hump are obtained by the prevention of GOX thinning and a deep dent profile.

A Novel T-Shaped Shallow Trench Isolation Technology

This paper describes a novel T-shaped shallow trench isolation (STI) technology, which has the same effective isolation length with conventional STI but significantly reduced aspect ratio. The T-shaped STI is formed using 2-step trench etches. After the formation of the 1st trench of a relatively low aspect ratio, oxide spacer is formed inside the trench sidewall. And the 2nd trench is made to ensure an effective isolation length. When T-shaped STI is filled with undoped silicate glass (USG) and high density plasma (HDP) oxide, the mouth of 2nd trench is closed by the overhang of filling materials so that the effective aspect ratio of T-shaped STI can be lowered. We evaluated the electrical characteristics of T-shaped STI. Also, we performed simulation of the stress distribution and the junction profile. T-shaped STI has shown comparable characteristics to conventional STI and no electrical or physical degradation was found. We have adopted this technology to 512 Mbit flash memory (0.5 µm cell pitch) and obtained excellent structural and electrical properties. In addition, we obtained the excellent gap filling ability even for the 1 Gbit flash memory (0.34 µm cell pitch) and beyond.

Progress in device isolation technology

This contribution gives a brief overview on the current status of device isolation technology. Starting with conventional shallow-trench-isolation (STI), the challenges introduced by this approach are outlined. Based on this discussion, the concept of the recently developed extended trench isolation gate technology (EXTIGATE) is presented. It will be shown that EXTIGATE not only provides a relief from the drawbacks of conventional STI processing, but also offers promising alternatives for front-end process integration, device optimization and specific applications.

Round-off of trench corner by post-cylindrical molecular pump sidewall oxidation for 0.25 μm and beyond technologies

A post-cylindrical molecular pump (CMP) sidewall oxidation (PCSWO) has been developed for the shallow trench isolation (STI) process of 0.25 μm and beyond complementary metal–oxide–semiconductor technologies. One of the most important factors of STI is a round-off of trench top corners without the loss of active area. The conventional STI process usually requires a wall oxidation after trench etch to round off and also an annealing to densify a gap-filled oxide. But PCSWO simplifies the STI process by applying sidewall oxidation and annealing simultaneously. The trench was filled with HDP oxide without the conventional wall oxidation after trench etch. After CMP, post-CMP wall oxide was thermally grown to round off the trench corner at the high temperature of 1100 °C. The high temperature wall oxidation has an annealing effect for HDP oxide, which releases a residual film stress. The anomalous subthreshold conduction of the shallow trench isolated metal–oxide–semiconductor field effect transistors as the so called “kink effect” due to field crowding at the active edge, was successfully eliminated even at the back bias of ±5 V. Isolation and diode characteristics of PCSWO-STI were comparable to those of the conventional STI. Gate oxide reliabilities of PCSWO-STI were similar to those of the conventional STI.

A Novel Shallow Trench Isolation with Mini-Spacer Technology

A new shallow trench isolation (STI) process with a mini-spacer at the masking nitride sidewall before silicon trench etching was proposed. With this mini-spacer, thicker corner liner oxide and a T-shaped trench oxide can be formed simultaneously. The issue of oxide-recess at STI corner can be effectively reduced and larger process window for subthreshold kink free device were obtained. The isolation capability and junction integrity were both improved as compared with those of the conventional STI process. Reverse narrow width effect as well as gate oxide integrity were also improved. This technology was employed for 0.13 µm complementary metal oxide silicon (CMOS) device fabrication.