Conventional LDMOS Research Articles

New folding lateral double diffused metal oxide semiconductor breaking silicon limit with ultra‐low specific on‐resistance

A new lateral double diffused metal oxide semiconductor (LDMOS) is proposed for the first time with the step oxide layer above the folding silicon substrate. Three technologies, including of the electric field modulation effect, majority carrier accumulation, and folding silicon, are applied simultaneously to the proposed LDMOS for improving the trade-off between the breakdown voltage (BV) and specific on-resistance (R on,sp). The majority carrier accumulation layer under the extended gate is formed in the folding silicon substrate during the on-state operation. The high-doping drift region can be depleted completely in the off-state, thanks to an additional electric field modulation, which is analogous to the super junction idea. The uniform lateral electric field has been obtained due to the new electric field peak to improve the trade-off between the BV and R on,sp. The proposed LDMOS shows the R on,sp of 0.32 mΩ cm2 with the BV of 62 V, which has broken the silicon limit relationship with R on,sp of 2.0 mΩ cm2 under the same BV in the conventional LDMOS. This is the previously reported lowest R on,sp with the BV of about 60 V.

Improving breakdown, conductive, and thermal performances for SOI high voltage LDMOS using a partial compound buried layer

A novel SOI LDMOS with a partial compound buried layer structure (P-CBL SOI) is proposed in this paper. The buried oxide layer at the source-side is replaced by a compound buried layer (CBL) of “top oxide-middle polysilicon-bottom oxide”, and the buried oxide layer at the drain-side is just as the conventional SOI LDMOS (C-SOI). Firstly, a new peak of electric field is introduced at the interface and the whole lateral electric field in the top silicon layer is modulated, resulting in a higher lateral BV. Secondly, impurity doping meeting the RESURF effect in the top silicon layer is higher because the top oxide is thinner than the conventional buried oxide layer, leading to a lower Ron,sp at the on-state and an enhanced vertical BV at the off-state. Finally, thermal conductivity of polysilicon is higher than that of SiO2, offering a lower self-heating effect. The influences of structure parameters on the devices performances are investigated. Compared with those of C-SOI LDMOS on the same top silicon layer of 4μm, buried dielectric layer of 4μm, and drift region of 40μm, BV of P-CBL SOI LDMOS is enhanced by 33.4%, Ron,sp is reduced by 37.4%, and the maximum temperature at the power of 1mW/μm is depressed by 13.3K, respectively.

Complete 3D-Reduced Surface Field Superjunction Lateral Double-Diffused MOSFET Breaking Silicon Limit

A new superjunction lateral double-diffused MOS with the semi-insulating poly silicon (SIPOS SJ-LDMOS) has been proposed in this letter, for the first time, with the complete three-dimensional reduced surface field (3D-RESURF). The SIPOS SJ-LDMOS along the three dimensions are subject to the electric field modulation, which achieves the complete 3D-RESURF effect. The simulated breakdown voltage (BV) for the unit length of the drift region is improved to 19.4 $\mathrm {V}/ \mu \text{m}$ . The drift region with the high concentration compared with the conventional LDMOS can be depleted completely in the OFF-state to obtain the high BV. Moreover, the majority carrier accumulation can be formed to further decrease $R_{\mathrm {\scriptscriptstyle ON},\textrm {sp}}$ (specific on resistance) during the ON-state operation. Three effects have been combined to SIPOS SJ-LDMOS for the superjunction ideal, electric field modulation and the majority carrier accumulation by SIPOS. The tradeoff between the BV and $R_{\mathrm {\scriptscriptstyle ON},\textrm {sp}}$ has been improved to break through the silicon limit. The results show that the experimental $R_{\mathrm {\scriptscriptstyle ON},\textrm {sp}}$ of SIPOS SJ-LDMOS is 18 $\text{m}\Omega \cdot \textrm {cm}^{2}$ with the tested BV of 376 V, which is less than that of 31.1 $\text{m}\Omega \cdot \textrm {cm}^{2}$ for the $N$ -buffer SJ-LDMOS with the simulated BV of 287 V, and far less than 71.8 $\text{m}\Omega \cdot \textrm {cm}^{2}$ for the conventional LDMOS with the simulated BV of 254 V for the same drift region length of 20 $\mu \text{m}$ .

A novel low specific on-resistance double-gate LDMOS with multiple buried p-layers in the drift region based on the Silicon-On-Insulator substrate

A novel double-gate SOI LDMOS with multiple buried p-layers in the drift region (MBP SOI LDMOS) is proposed in this paper. MBP SOI LDMOS has two gates, the planar gate and the trench gate. The big feature of MBP LDMOS is the multiple buried p-layers with intervals in the drift region which is an arithmetic progression and decreases successively. Firstly, double gates of the structure form dual current conduction channels, leading to a low specific on-resistance (Ron,sp). Secondly, the multiple buried p-layers form a more significant triple RESURF effect, which not only increases the drift doping concentration but also modulates the electric field of the drift region, resulting in a low Ron,sp and a high breakdown voltage (BV). MBP SOI LDMOS is thus owning a reduced Ron,sp and an improved BV. The effects of structure parameters on the device performances are investigated. Compared with the conventional SOI LDMOS, the Ron,sp of MBP SOI LDMOS is reduced by 52.5% with BV increasing by 36.4% at the same 16-μm-drift region.

Omega shape channel LDMOS: A novel structure for high voltage applications

A new device structure for high breakdown voltage and low specific on resistance of the LDMOS device is proposed in this paper. The main idea in the proposed structure is using omega shape channel. The benefits of omega shape channel could be determined by extending depletion region in the drift region that causes low specific on resistance. Also, uniform horizontal electric field would be achieved that results in high breakdown voltage. The proposed structure is called Omega-shape Channel LDMOS (OCH-LDMOS). The simulation with two dimensional ATLAS simulator shows that the breakdown voltage increases to 712V from 243V of the conventional LDMOS at 12µm drift length. Also, effective values of doping, length, and depth of Ω-shape channel are investigated.

High performance DCTG-LDMOS on InGaAs for RF power amplifier applications

In this work, we propose a new dual-channel trench-gate LDMOS (DCTG-LDMOS) structure on emerging InGaAs material by incorporating trenches in the planar technology. The gate electrode of DCTG-LDMOS is placed vertically in a trench at the centre of unit cell to create two channels in the p-base which carry drain current in parallel. This not only enhances the drain current (ID) but also reduces specific on-resistance (Ron,sp) and improves the peak transconductance (gm) resulting higher cut-off frequency (ft) and maximum oscillation frequency (fmax). Further, other two identical trenches filled with Al2O3 are symmetrically located on both sides of p-base to enhance reduced-surface-field (RESURF) effect leading to higher breakdown voltage (Vbr). Based on two-dimensional numerical simulations, the DCTG-LDMOS is demonstrated to achieve more than 2 times increase in ID, 66% reduction in Ron,sp, 73% higher gm, 69% improvement in Vbr, and 23% increase in ft and fmax over the conventional LDMOS.

Thin silicon layer SOI power device with linearly-distance fixed charge islands**Project supported by the Guangxi Natural Science Foundation of China (No. 2013GXNSFAA019335), the Guangxi Department of Education Project (No.201202ZD041), the China Postdoctoral Science Foundation Project (Nos. 2012M521127, 2013T60566), and the National Natural Science Foundation of China (Nos. 61361011, 61274077, 61464003).

A new high-voltage LDMOS with linearly-distanced fixed charge islands is proposed (LFI LDMOS). A lot of linearly-distanced fixed charge islands are introduced by implanting the Cs or I ion into the buried oxide layer and dynamic holes are attracted and accumulated, which is crucial to enhance the electric field of the buried oxide and the vertical breakdown voltage. The surface electric field is improved by increasing the distance between two adjacent fixed charge islands from source to drain, which lead to the higher concentration of the drift region and a lower on-resistance. The numerical results indicate that the breakdown voltage of 500 V with Ld = 45 μm is obtained in the proposed device in comparison to 209 V of conventional LDMOS, while maintaining low on-resistance.

A new technique in LDMOS transistors to improve the breakdown voltage and the lattice temperature

A new technique for high breakdown voltage of the LDMOS device is proposed in this paper. The main idea in the proposed technique is to insert the P+ silicon windows in the buried oxide at the interface of the n-drift to improve the breakdown voltage, electric field and maximum lattice temperature. The proposed structure is called as P+ window LDMOS (PW-LDMOS). It is shown by extending the depletion region between the P+ windows and the n-drift region, the breakdown voltage of PW-LDMOS increases to 405V from 84V of the conventional LDMOS on 1µm silicon layer and 2µm buried oxide layer. Also, effective values of doping, length, and depth of P+ window are investigated in the breakdown voltage. Moreover, a self-heating-effect is alleviated by the silicon windows in comparison with the conventional LDMOS. All the achieved results have been extracted by two-dimensional and two-carriers simulator ATLAS.

A novel high figure-of-merit SOI SJ LDMOS with ultra-strong charge accumulation effect**Project supported by the National Natural Science Foundation of China (Nos. 61176069, 61376079) and the Program for New Century Excellent Talents in University of Ministry of Education of China (No. NCET-11-0062).

A novel silicon-on-insulator (SOI) super-junction (SJ) LDMOS with an ultra-strong charge accumulation effect is proposed. It has two key features: an assisted-accumulation trench-type extending gate (TEG) with a high-k (HK) dielectric and a step-doped N pillar (TEG-SD SJ LDMOS). In the on-state, electrons accumulate at the sidewall of the HK dielectric from the source to the drain by the TEG. Furthermore, the high permittivity of the HK dielectric leads to an ultra-strong charge accumulation effect. As a result, an ultra-low resistance current path is formed. The specific on-resistance (Ron, sp) is thus greatly reduced and is independent of the drift doping concentration. In the off-state, the step-doped N pillar effectively suppresses the substrate-assisted depletion effect by charge compensation. Moreover, the reshape effect of the HK dielectric and the new electric field (E-field) peak introduced by the step-doped N pillar enhance the drift region E-field. Hence, the BV is improved. Simulation indicates that the TEG-SD SJ LDMOS achieves an extremely low Ron, sp of 1.06 mΩ·cm2 and a BV of 217 V. Compared with the conventional SJ LDMOS, the TEG-SD SJ LDMOS decreases the Ron, sp by 77.5% and increases the BV by 33%, exhibiting a high figure of merits (FOM = BV2/Ron, sp) of 44 MW/cm2.

New SOI power device with multi-region high-concentration fixed interface charge and the model of breakdown voltage**Project supported by the State Key Laboratory of Electronic Thin Films and Integrated Devices of China (Grant No. KFJJ201205), the Department of Education Project of Guangxi Province, China (Grant No. 201202ZD041), the Postdoctoral Science Foundation Project of China (Grant Nos. 2012M521127 and 2013T60566), and the

A new SOI power device with multi-region high-concentration fixed charge (MHFC) is reported. The MHFC is formed through implanting Cs or I ion into the buried oxide layer (BOX), by which the high-concentration dynamic electrons and holes are induced at the top and bottom interfaces of BOX. The inversion holes can enhance the vertical electric field and raise the breakdown voltage since the drain bias is mainly generated from the BOX. A model of breakdown voltage is developed, from which the optimal spacing has also been obtained. The numerical results indicate that the breakdown voltage of device proposed is increased by 287% in comparison to that of conventional LDMOS.

Ultralow specific on-resistance high voltage trench SOI LDMOS with enhanced RESURF effect

A RESURF-enhanced high voltage SOI LDMOS (ER-LDMOS) with an ultralow specific on-resistance (Ron, sp) is proposed. The device features an oxide trench in the drift region, a P-pillar at the sidewall of the trench, and a buried P-layer (BPL) under the trench. First, the P-pillar adjacent to the P-body not only acts as a vertical junction termination extension (JTE), but also forms a vertical reduced surface field (RESURF) structure with the N-drift region. Both of them optimize the bulk electric field distributions and increase the doping concentration of the drift region. Second, the BPL together with the N-drift region and the buried oxide layer (BOX) exhibits a triple-RESURF effect, which further improves the bulk field distributions and the doping concentration. Additionally, multiple-directional depletion is induced owing to the P-pillar, the BPL, and two MIS-like structures consisting of the N-drift region combined with the oxide trench and the BOX. As a result, a significantly enhanced-RESURF effect is achieved, leading to a high breakdown voltage (BV) and a low Ron, sp. Moreover, the oxide trench folds the drift region in the vertical direction, resulting in a reduced cell pitch and thus Ron, sp. Simulated results show that the ER-LDMOS improves BV by 67% and reduces Ron, sp by 91% compared with the conventional trench LDMOS at the same cell pitch.

Novel 700 V high-voltage SOI LDMOS structure with folded drift region

A new high-voltage LDMOS with folded drift region (FDR LDMOS) is proposed. The drift region is folded by introducing the interdigital oxide layer in the Siactive layer, the result of which is that the effective length of the drift region is increased significantly. The breakdown characteristic has been improved by the shielding effect of the electric field from the holes accumulated in the surface of the device and the buried oxide layer. The numerical results indicate that the breakdown voltage of 700 V is obtained in the proposed device in comparison to 300 V of conventional LDMOS, while maintaining low on-resistance.

New Superjunction LDMOS Breaking Silicon Limit by Electric Field Modulation of Buffered Step Doping

A new superjunction LDMOS (SJ-LDMOS) is proposed with the step doping buffered layer under the SJ layer to obtain the low loss for the high-voltage region. The substrate-assisted depletion effect, which results from the p-type substrate for the n-channel SJ-LDMOS, has been eliminated by the step doping buffer layer. By the effect of the electric field modulation, a more uniform lateral electric filed is obtained due to the new high-electric field peaks introduced by the buffered step doping, which improves the breakdown voltage (BV) and average lateral electric field. Using ISE simulation, the BV of proposed SJ-LDMOST is increased by ~50% than that of the conventional LDMOS, and improved by ~32% than that of buffered SJ-LDMOS. The lateral average electric field is increased to 19 V/μm in the high-voltage region The experimental RON,sp of the proposed SJ-LDMOS is 241 mΩ · cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with a BV of 368 V, breaking the silicon limit relationship for R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> of 71.8 mΩ · cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with the BV of 242 V in the conventional LDMOS with the same drift region length The merit of BV/R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> is 15.3 for the proposed SJ-LDMOS compared with that of 3.4 for the conventional LDMOS.

New folding lateral double-diffused metal-oxide-semiconductor field effect transistor with the step oxide layer

In order to design the power devices with the low loss required for the power integrated circuits (PIC), a new folded silicon LDMOS with the folding step oxide layer (SOFLDMOS) is proposed in this paper for the first time. In this structure, the step oxide layer is covered on the folded silicon surface with a periodic distribution. The surface electric field is optimized to be uniform by introducing a new electric field peak due to the electric field modulation effect by the step oxide layer. The breakdown voltage is improved to solve the breakdown voltage limitation problem in FALDMOS. Obtained in virtue of the ISE simulation are the results that the silicon limit is broken by applying the effects of the electric field modulation, accumulation of majority carriers, and conductive silicon region multiplier in the proposed SOFLDMOS. The saturation current of the drain electron is increased by about 3.4 times compared with that of the conventional LDMOS. When the breakdown voltage is 62 V, an ultra-low specific on-resistance of 0.74 mΩ·cm2 is obtained, which is far less than 2.0 mΩ·cm2 in the conventional LDMOS with the same breakdown voltage. The low loss requirements is achieved for the PIC with the low voltage region by the proposed SOFLDMOS.

New super junction lateral double-diffused metal-oxide-semiconductor field-effect transistor with the P covered layer

In order to design the lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOS) with low loss required for a power integrated circuit, a new super junction LDMOS with the P covered layer which is based on the existing N buffered super junction LDMOS is proposed in this paper for the first time. The key feature of the proposed structure is that the P-type covered layer is partly above the N-type of the super junction layer, which is different from the N buffered super junction LDMOS. In this structure, the specific on-resistance of the device is reduced by using the high doped super junction layer; the problem of the substrate-assisted depletion which is produced due to the P-type substrate of the N-channel super junction LDMOS is eliminated by completely compensating for the charges of the N-type buffered layer and the P-type covered layer, thus improving the breakdown voltage. The charges of the N-type and P-type pillars are depleted completely. A new transmission path at the on-state is formed by N buffered layer to reduce the specific on-resistance, which is similar to the N buffered super junction LDMOS. However, the effect of N-type buffered layer of N buffered super junction LDMOS is not fully used. The drift region of the device is further optimized by the proposed device to reduce the specific on-resistance. The charge concentration of the N-type buffered layer in the proposed device is improved by the effect of charge compensation of the P covered layer. It is clear that high breakdown voltage and low specific on-resistance are realized in the proposed device by introducing the P-type covered layer and the N-type buffered layer. The results of the 3 D-ISE software suggest that when the drift region is on a scale of 10 μm, a specific on-resistance of 4.26 mΩ·cm2 obtained from P covered super junction LDMOS by introducing P covered layer and N buffered layer is reduced by about 59% compared with that of conventional super junction LDMOS which is 10.47 mΩ·cm2, and reduced by about 43% compared with that of N Buffered super junction LDMOS which is 7.46 mΩ·cm2.

Thin layer oxide in the drift region of Laterally double-diffused metal oxide semiconductor on silicon-on-insulator: A novel device structure enabling reliable high-temperature power transistors

In this paper a new lateral double diffused metal oxide semiconductor (LDMOS) transistor on silicon-on-insulator (SOI) technology is reported. In the proposed structure a trench oxide in the drift region is reformed to reduce surface temperature. In the LDMOS devices one way for achieving high breakdown voltage is incorporating the trench oxide in the drift region. But, this strategy causes high lattice temperature in the device. So, the middle of the trench oxide in the drift region is etched and filled with the silicon to have higher thermal conductivity material and reduce the lattice temperature in the drift region. The simulation with two-dimensional ATLAS simulator shows that the novel thin trench oxide in the n-drift region of LDMOS transistor (TT-LDMOS) have lower maximum lattice temperature with an acceptable breakdown voltage in respect to the conventional LDMOS (C-LDMOS) structure with the trench oxide in the drift region. So, TT-LDMOS can be a reliable device for power transistors.

New Superjunction LDMOS With the Complete Charge Compensation by the Electric Field Modulation

A new superjunction (SJ) LDMOS has been proposed with the complete charge compensation by the electric field modulation in this letter for the first time. The substrate-assisted depletion, produced due to the p-type substrate for the n-channel SJ-LDMOS, has been eliminated by the electric field modulation produced due to the step n-type buffered layer. The charge for the n- and p-type drifts has been depleted completely. Moreover, a new electric field peak has been introduced in the surface electric field distribution, which makes the lateral surface electric field uniform. The breakdown voltage has been improved for the new SJ-LDMOS compared with the conventional SJ-LDMOS because of the uniform surface electric field. By simulating and experimental results, the breakdown voltage of the new SJ-LDMOS with the electric field modulation has been increased by ~49% compared with the conventional LDMOS, and improved by ~30% compared with the conventional SJ-LDMOS.

A new high-side and low-side LDMOST with a selective buried layer in the substrate

In this article, a novel low- and high-side lateral double-diffused metal–oxide–semiconductor field-effect-transistor (LDMOST) with an n-type selective buried layer (SBL-LDMOST) in a p-type substrate is presented. When the device operates in the high-side mode, the buried layer prevents vertical punch-through and then the vertical breakdown voltage (BV) is enhanced. When the device operates in the low-side mode, the depleted space-charges in the selective buried layer modulate the bulk electric field and then enhance the substrate to sustain higher reverse voltage. Simulation results show that the low-side BV increases from 585V of the conventional LDMOST to 688V and the high-side BV increases from 962V to 1791V at the same 60μm drift region lengths condition. In addition, when operating in the high-side mode, the drive-current is not alleviated due to drift region immunity from depletion.

A novel LDMOS with a junction field plate and a partial N-buried layer

A novel lateral double-diffused metal—oxide semiconductor (LDMOS) with a high breakdown voltage (BV) and low specific on-resistance (Ron.sp) is proposed and investigated by simulation. It features a junction field plate (JFP) over the drift region and a partial N-buried layer (PNB) in the P-substrate. The JFP not only smoothes the surface electric field (E-field), but also brings in charge compensation between the JFP and the N-drift region, which increases the doping concentration of the N-drift region. The PNB reshapes the equipotential contours, and thus reduces the E-field peak on the drain side and increases that on the source side. Moreover, the PNB extends the depletion width in the substrate by introducing an additional vertical diode, resulting in a significant improvement on the vertical BV. Compared with the conventional LDMOS with the same dimensional parameters, the novel LDMOS has an increase in BV value by 67.4%, and a reduction in Ron.sp by 45.7% simultaneously.

A low specific on-resistance SOI LDMOS with a novel junction field plate

A low specific on-resistance SOI LDMOS with a novel junction field plate (JFP) is proposed and investigated theoretically. The most significant feature of the JFP LDMOS is a PP—N junction field plate instead of a metal field plate. The unique structure not only yields charge compensation between the JFP and the drift region, but also modulates the surface electric field. In addition, a trench gate extends to the buried oxide layer (BOX) and thus widens the vertical conduction area. As a result, the breakdown voltage (BV) is improved and the specific on-resistance (Ron,sp) is decreased significantly. It is demonstrated that the BV of 306 V and the Ron,sp of 7.43 mΩ·cm2 are obtained for the JFP LDMOS. Compared with those of the conventional LDMOS with the same dimensional parameters, the BV is improved by 34.8%, and the Ron,sp is decreased by 56.6% simultaneously. The proposed JFP LDMOS exhibits significant superiority in terms of the trade-off between BV and Ron,sp. The novel JFP technique offers an alternative technique to achieve high blocking voltage and large current capacity for power devices.