Conventional Gate Driver Research Articles

A Novel Driving Current Control Approach in Enhanced Current-Source Gate Driver

Active gate drivers (AGDs) get popular by their capability to flexibly control the switching behavior of power transistor. State-of-the-art AGDs need to adopt extensive driving switches, resistors or additional voltage or current sources which significantly increase the cost, size and complexity of gate driver. To overcome this bottleneck, an enhanced inductor-based current source gate driver (ECSGD) with well controlled gate driving current and fast driving current transition is proposed in this paper. Driving current is controlled by switching between different resonant networks within a pre-settled hysteresis window to solve the poor gate driving current regulation limitation of conventional inductor-based current source gate driver. Driving current transition speed is also accelerated by internal supply voltage boosting function. The design prototype demonstrates the driving current control of 2A with hysteresis window of 0.3A. The driving current transition time is shortened by more than 30% with VD1 boosted from 15V to 25V. Hence, the ECSGD can be used as an AGD with simple structure, high control accuracy and fast response speed.

An experimental study on switching waveform design with gate charge control for power MOSFETs

Designing switching waveforms is a technique for mitigating a trade-off between loss and noise in switching power devices. A novel and simple method has been proposed to compute the gate waveform to realize a designed switching waveform. The gate current pulse is calculated to eliminate the deviation between the designed target waveform and the observed waveform at the moment using a linear combination of drain-source voltage or drain current responses to a small gate charge pulse train. In this paper, a verification system including a simple gate current pulse generator consisting of operational amplifiers and transistors was built together with a conventional voltage source gate driver, and validation of the proposed method was experimentally performed using the drain-source voltage waveform of a Si MOSFET during the turn-off phase. Applying the obtained drain-source voltage responses to the proposed method, the gate current pulse to be added to realize a given target waveform was calculated and superimposed on the output of the gate driver. The measured drain-source voltage waveform was well-matched to the target. In addition, the impact of the drain current values on the design of the drain-source waveform was verified.

High Bandwidth Active Gate Driver for Simultaneous Reduction of Switching Surge and Switching Loss of SiC-MOSFET

This study investigates an active gate driver (AGD) for an SiC-MOSFET. The source current feedback type AGD utilizes the induced voltage of the source wire inductance as a negative feedback signal to regulate the source current di/dt. Recent improvements in the switching performance of the AGD is limited due to the feedback system bandwidth. In this paper, a high bandwidth current feedback type power operational amplifier is applied as the gate drive circuit. Switching characteristics of the conventional resistive gate driver and AGD are experimentally investigated via a double pulse test setup. The switching setup condition is 700 V / 80 A. This paper describes the development of the AGD circuit and experimental results. The over-shoot and ringing of the Vds and Is are reduced using the AGD. Moreover, the switching loss is simultaneously reduced.

Integrating 10-kV SiC MOSFET Into Battery Energy Storage System With a Scalable Converter-Based Self-Powered Gate Driver

In the hardware design of battery energy storage system (BESS) interface, in order to meet the high-voltage requirement of grid side, integrating 10-kV silicon-carbide (SiC) MOSFET into the interface could simplify the topology by reducing the component count. However, the conventional gate driver design is challenging and inextensible in BESS, since the high-voltage rating and high dv/dt bring the requirements of high-voltage isolation and low common-mode capacitance. Therefore, in this article, a scalable converter-based self-powered (SCS) gate driver is further proposed. A 5-kV input power extracting converter based on a voltage-balanced SiC MOSFET stack is constructed to self-power the gate driver, which exhibits simplification of basic topology and sufficient gate driver power handling capability regardless of the switching requirement of main loop power device. Besides this, the power extracting converter is designed to act as a clamping resistor-capacitor-diode (RCD) snubber circuit, which makes the SCS gate driver scalable to the series connection of power devices. Analysis and design consideration are given in detail, followed by the experimental verification using 10-kV/10-A SiC MOSFETs.

A Novel Isolated Resonant Gate Driver With Adjustable Duty Ratio for SiC MOSFET

Resonant gate driver is a promising technique to save gate driver loss at high switching frequencies to further promote the integration level of gate driver with power modules. State-of-the-art isolated resonant gate drivers (RGDs) have to keep duty ratio fixed at 0.5 to avoid transformer saturation, which significantly limits the practical applications. A new isolated RGD (IRGD) with adjustable duty ratio to drive silicon carbide (SiC) MOSFET is proposed in this article by employing switching period expansion technique with a dual-secondary transformer. Transformer secondary windings are involved in the turn-on and turn-off processes alternatively and are switched at the falling edge of each input driving cycle. The effective switching frequency at gate driver transformer is reduced to 1/2 to further save power losses at high switching frequencies. This article further discusses the optimal damping approach to suppress <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$v_{\mathrm {gs}}$ </tex-math></inline-formula> overshoot and oscillation due to an adjacent second driving stage brought by parasitic gate resistor for IRGDs. The proposed IRGD is built with printed circuit board (PCB) integrated planar transformers, designed at leakage inductance of 303 nH with primary-side silicon (Si) devices and secondary bidirectional gallium nitride (GaN) devices. The duty ratio is proven to be adjusted from 0.15 to 0.9. The power consumption of the prototype is 0.883 W at 500 kHz and 1.473 W at 1 MHz driving a 900-V SiC device with 87-nC gate charge, which is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6\times $ </tex-math></inline-formula> less power consumed than a conventional gate driver (CGD). The adopted SiC power device achieves dv/dt on of 18 V/ns and dv/dt off of 35 V/ns with the proposed IRGD.

Comparisons on Different Innovative Cascode GaN HEMT E-Mode Power Modules and Their Efficiencies on the Flyback Converter

The conventional cascode structure for driving depletion-mode (D-mode) gallium nitride (GaN) high electron mobility transistors (HEMTs) raises reliability concerns. This is because of the possibility of the gate to source voltage of the GaN HEMT surging to a negative voltage during the turn off transition. The existing solutions for this problem in the literature produce additional drawbacks such as reducing the switching frequency or introducing many additional components. These drawbacks may outweigh the advantages of using a GaN HEMT over its silicon (Si) alternative. This paper proposes two innovative gate drive circuits for D-mode GaN HEMTs—namely the GaN-switching based cascode GaN HEMT and the modified GaN-switching based cascode GaN HEMT. In these schemes, the Si MOSFET in series with the D-mode GaN HEMT is always turned on during regular operation. The GaN HEMT is then switched on and off by using a charge pump based circuit and a conventional gate driver. Since the GaN HEMT is driven independently, the highly negative gate-to-source voltage surge during turn off is avoided, and in addition, high switching frequency operation is made possible. Only two diodes and one capacitor are used in each of the schemes. The application of the proposed circuits is experimentally demonstrated in a high voltage flyback converter, where more than 96% efficiency is obtained for 60 W output load.

A gate driver circuit with the two-stage pre-charge structure for in-cell touch panels

Due to the charge leakage during the touch sensing period and the threshold voltage shift of the driving thin-film transistors (TFTs), the conventional gate driver circuits suffer from poor stability for in-cell touch displays with an increased touch reporting rate. This paper shows a new gate driver circuit, consisting of a two-stage pre-charge structure, which can reduce the charge leakage during the touch sensing period and suppress the threshold voltage shift of the driving TFTs. Simulation results demonstrate that, the rising and falling time differences between adjacent stages are 9.3% and 1.6% for the conventional and the proposed gate driver circuit, respectively. In the case that the threshold voltage of key TFT shifts by +10 V, the rising and falling time degradation ratios are 120% and 2.4% for the conventional and the proposed gate driver circuit, respectively. Therefore, the proposed gate driver circuit is stable for in-cell touch panels with a high touch reporting rate.

Parasitic-Based Active Gate Driver Improving the Turn-On Process of 1.7 kV SiC Power MOSFET

This article discusses an active gate driver for a 1.7 kV/325 A SiC MOSFET module. The main purpose of the driver is to adjust the gate voltage in specified moments to speed up the turn-on cycle and reduce the amount of dissipated energy. Moreover, an adequate manipulation of the gate voltage is necessary as the gate current should be reduced during the rise of the drain current to avoid overshoots and oscillations. The gate voltage is switched at the right moments on the basis of the feedback signal provided from a measurement of the voltage across the parasitic source inductance of the module. This approach simplifies the circuit and provides no additional power losses in the measuring circuit. The paper contains the theoretical background and detailed description of the active gate driver design. The model of the parasitic-based active gate driver was verified using the double-pulse procedure both in Saber simulations and laboratory experiments. The active gate driver decreases the turn-on energy of a 1.7 kV/325 A SiC MOSFET by 7% comparing to a conventional gate driver (VDS = 900 V, ID = 270 A, RG = 20 Ω). Furthermore, the proposed active gate driver lowered the turn-on cycle time from 478 to 390 ns without any serious oscillations in the main circuit.

Suppressing Voltage Spikes of MOSFET in H-Bridge Inverter Circuit

Power electronics devices are made from semiconductor switches such as thyristors, MOSFETs, and diodes, along with passive elements of inductors, capacitors, and resistors, and integrated circuits. They are heavily used in power processing for applications in computing, communication, medical electronics, appliance control, and as converters in high power DC and AC transmission in what is now called harmonized AC/DC networks. A converter’s operation is described as a periodic sequencing of different modes of operation corresponding to different topologies interfaced to filters made of passive elements. The performance of converters has improved considerably using high switching frequency, which leads to a significant improvement in a power converter’s performance. However, the high dv/dt through a fast-switching transient of the MOSFET is associated with parasitic components generating oscillations and voltage spikes having adverse effects on the operation of complementary switches, thereby affecting the safe operation of the power devices. In this paper, the MOSFET gate-driver circuit performance is improved to suppress the H-Bridge inverter’s voltage spikes. The proposed technique is a simple improvement to the gate driver based on the IR2112 driver (IC) by adding a capacitor to attenuate the effect of parasitic components and the freewheeling current, suppressing the negative voltage spikes. This paper’s main contribution is to improve the gate driver circuit’s capability for suppressing the voltage spikes in the H-Bridge inverter. The improved gate driver circuit is validated experimentally and is compared with the conventional gate driver. The experimental results show that the proposed technique can effectively suppress the MOSFET’s voltage spikes and oscillations.

A Multi-Level Gate Driver for Crosstalk Suppression of Silicon Carbide MOSFETs in Bridge Arm

In high frequency applications of silicon carbide (SiC) MOSFET, it is easy to be affected by parasitic parameters where crosstalk phenomenon in bridge arm will occur. This paper proposes a novel multi-level gate driver which can suppress the crosstalk phenomenon of the SiC MOSFETs in bridge arm. An auxiliary MOSFET branch between the gate and source of SiC MOSFET is adopted to generate negative and zero gate voltage when SiC MOSFET is turned off. The negative gate voltage may reduce the positive gate crosstalk voltage, and zero gate voltage may reduce negative gate crosstalk voltage. Both the simulations and experiments are carried out to verify the feasibility and high performance of the proposed multi-level gate driver. Compared to the conventional gate driver, the proposed multi-level gate driver reduces the positive crosstalk voltage to -2.2V, and the negative crosstalk voltage to -4.4V, respectively.

A simple gate driver design for GaN-based switching devices with improved surge voltage and switching loss at 1 MHz operation

In power electronics, the impedance of reactance components increases proportionally with frequency; therefore, the sizes of reactance components can be reduced by increasing the switching frequency. Gallium nitride (GaN)-based devices have received significant attention in high-frequency applications because the figure-of-merit of GaN is superior to that of silicon (Si). However, for high-frequency operation, a trade-off relationship between the surge voltage induced by parasitic inductances, and the switching loss becomes significant. Therefore, in this study, we propose a gate driver that improves the trade-off relationship. This gate driver was obtained via the addition of simple logic circuits and capacitors to a conventional gate driver. The effectiveness of our proposed circuit was verified via SPICE simulations with Cadence Spectre using 180 nm CMOS technology. The simulation results show that by operating at 1 MHz, this circuit can help reduce the surge voltage by 12.2% and the switching loss by 14.3%.

Novel driver circuit for switching performance improvements in SiC MOSFETs

Silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) are expected to be an attractive replacement for Si MOSFETs in high power applications due to their high blocking voltage, high switching speed, and low switching losses. However, a high switching speed can lead to voltage and current overshoot as well as oscillation during the switching process, which results in additional losses and severe electromagnetic interference. It can also exceed the limit of the SiC MOSFET and cause irreversible damage to the device. Based on an analysis of the SiC MOSFET switching process voltage and current overshoot and oscillation generation mechanism, a voltage-injected active gate driver (AGD) was proposed. The proposed AGD can suppress the voltage and current overshoot and oscillation by injecting voltage into the gate of the SiC MOSFET during specific switching stages. Experimental results show that when compared with the conventional gate driver (CGD), the proposed AGD can suppress the voltage and current overshoot peaks by 16% and 12%, while reducing voltage and current oscillation times by 58% and 31%, respectively.

A Pre-Bootstrapping Method for Use in Gate Driver Circuits to Improve the Scan Pulse Delay of High-Resolution TFT-LCD Systems

A new pre-bootstrapping method (PBM) using hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) for a gate driver that is used in high-frame-rate or high-resolution displays is presented in this article. The PBM utilizes the capacitive coupling effect to bootstrap the gate voltage of the driving TFT twice to improve the insufficient field-effect mobility of the a-Si:H TFT without the need to enlarge the driving TFT. To investigate the driving capability of an a-Si:H TFT varying with the gate bias, a simulation model, based on the measured transfer curves of an a-Si:H TFT, is developed. Based on the specifications of 5.9-in panel with full high-definition resolution and 60 Hz frame rate, gate drivers with different structures are fabricated and compared. The experimental results demonstrate that the rising and the falling time of the output waveform generated from the gate driver with PBM are 45.21% and 32.04% shorter than those of the conventional gate driver. Furthermore, under a doubling of loadings, a 50 kHz clock frequency, and operation at −20 °C, the proposed PBM improve the performance of a gate driver. During an accelerated lifetime test at 85 °C, the gate driver with PBM can generate stable output waveforms for 864 h, verifying its long-term reliability.

A Time-Segmented Resonant Gate Driver Analysis for Loss, Speed, and SiC Switching Performance Trioptimization

A novel “time-segmented” transient analysis approach is proposed in this article for resonant gate driver (RGD) with triaspect optimization. RGD is a more advanced solution in high-frequency and high-power-density applications than the conventional gate driver (CGD). RGD will achieve lower gate driver loss, faster driving speed, and better SiC switching characteristics. However, the majority of current works on RGD only focused on gate driver loss and ignored its effect on power transistors' switching behavior. The characteristics of RGD are not well understood and modeled due to the ignorance of nonlinear components, such as power transistor's nonlinear input capacitor and nonlinear resonant intervals, and driving resistances. All of those result in false estimation of switching time and energy, which will cause underdesign of gate driver power supply and overdesign of resonant inductor. To fully investigate the potential of RGD, a “time-segmented” analysis approach proposed in this article utilizes the second-order equivalent circuit with actual switching transients. Different equivalent input capacitors are adopted for each segment. The impacts of the resonant inductor and gate resistor are studied. An optimized resonant inductor design is summarized by considering the three aspects mentioned earlier. Based on these, a full-bridge series RGD is designed for SiC power transistors. Compared with CGD, RGD can realize a 25% reduction in power consumption and 75.5% faster driving time. The designed RGD also improves SiC's di/dt and dv/dt up to 32%.

Realization of an IGBT Gate Driver With Dualphase Turn-On/Off Gate Control

Adding passive components in a conventional IGBT gate driver is a simple method to reduce transient current/voltage spikes during switching, but the extra devices and power loss make them less attractive. Alternatively, active gate drivers can improve the switching behavior, but are limited to specific devices and applications from the increased complexity of functions and feedback topology. This article reports a simple design for a general purpose gate driver methodology to reduce the peak reverse recovery current and over-voltage. The proposed topology was verified using a foundry 0.25- $\mu \text{m}$ BCD technology and experimental testing Remarkable improvements of crucial current overshoot during turn-on, voltage overshoot during turn-off, and the associated switching loss are demonstrated using novel dual-phase turn-on and turn-off gate controls.

Prediction Method of Driving Strategy of High-Power IGBT Module Based on MEA-BP Neural Network

An insulated gate bipolar transistor (IGBT) driver is crucial for improving the reliability of a power electronics system. This paper proposes a method for predicting the optimal driving strategy of high-power IGBT module based on backpropagation neural network optimized by the mind evolutionary algorithm in order to solve the problem of compromise among switching loss, switching time and overshoot and achieve a good driving effect. The three regions of switching transitions are analyzed based on the switching characteristics of the IGBT module. Neural networks are established to predict turn-on and turn-off driving strategies for variable gate resistance active gate driver of the IGBT module. The mind evolutionary algorithm is used to optimize the weights and biases of the neural networks so that the optimal weights and biases can be obtained. In order to verify the effectiveness of the driving strategy prediction method proposed in this paper, experiments are carried out for 4500V/900A the IGBT module. Compared to the conventional gate driver, the predicted driving strategies reduce the turn-on energy loss, turn-on time, overcurrent, comprehensive evaluation method, turn-on delay time and tail voltage duration by 59.31%, 46.38%, 36.99%, 65.65%, 1.9 μs, 2.9 μs, respectively. It was also found that the Planar-IGBT turn-off process was rarely affected by the gate resistance. The proposed method in this paper can be used not only for the guidance of the driving strategy determination of high-power the IGBT module driver, but also for the driver circuit improvement in the design process.

An Investigation of Gate Voltage Oscillation and its Suppression for SiC MOSFET

Silicon Carbide (SiC) MOSFET has undergone a rapid development and commercialization in recent years due to its superior features. However, the mainstream commercial SiC MOFESTs are often fitted to packages that are previously designed for silicon-based devices, which brings oscillation issues at faster switching speed. This paper investigates the gate oscillation based on the parasitic parameter analysis of equivalent SiC MOSFET circuit, where the influences of di/dt and dv/dt are discussed and compared. Moreover, the paper recommends a guideline for the acceptable gate oscillation for SiC MOSFET based on the data from manufacturers and carries out detailed comparisons of the conventional gate driver tuning methods. It is found that the external gate-source capacitor provides better switching performance and gate oscillation suppression than the tuning of gate resistor. The analysis and the switching performance are verified from the experimental results based on Cree CAS300M12BM2 SiC MOSFET Module.

A Multilevel Gate Driver of SiC mosfets for Mitigating Coupling Noise in Bridge-Leg Converter

Silicon carbide (SiC) devices can significantly increase power efficiency, temperature reliability, power capacity, and power density because of their outstanding characteristics. Nevertheless, in the bridge-leg configuration of a power converter, the high-speed switching capability of SiC mosfet s is often restricted by the coupling noise between high-side mosfet and low-side mosfet . The coupling noise caused by high ${dv/dt}$ and ${di/dt}$ in switching transient will increase the switching loss and the risk of mosfet breakdown. In order to completely take advantage of the superior feature of SiC mosfet s, a novel multilevel gate driver is proposed in this article to mitigate the coupling noise effectively. Compared to the conventional gate drivers, the proposed gate driver adds a capacitor, an auxiliary mosfet , a Zener diode, and two resistors to regulate the turn- off voltage bias felicitously. In this article, the operation principle of the proposed gate driver is first introduced, to the best of our knowledge. Moreover, to obtain the circuit parameters accurately, a series of formulas have also been derived by equivalent circuit models. A 230-V/4.6-A synchronous buck converter based on SiC mosfet s is successfully experimented to verify this proposed gate driver.

Self-Adaptive Active Gate Driver for IGBT Switching Performance Optimization Based on Status Monitoring

Compared to the conventional gate driver for the insulated gate bipolar transistor (IGBT), the active gate driver (AGD) not only reduces the switching delay but also suppresses voltage or current overshoot, however, at the expense of increasing the switching losses unavoidably. In this article, a self-adaptive active gate driver (SAGD) is proposed to further optimize IGBT switching performance, which is particularly suitable for applications where the load current varies over time or the dc bus voltage is changed. Since in such applications, AGD with fixed overshoot suppression ability will cause unnecessary switching loss, especially when the load current or the dc bus voltage is low. In contrast, with neither A/D nor D/A converters applied, the proposed SAGD indirectly detects the load current and dc bus voltage as time quantities, based on status monitoring, then self-adaptively chooses the optimal gate resistance increment online during the specific voltage or current rising phase. In this way, the current or voltage with overshoot is suppressed to be inside the safe operation area of IGBT while the switching loss is minimized, thus a better tradeoff between overshoots and switching losses is achieved. Finally, the feasibility of the proposed SAGD is verified by experiments.

A Novel Active Gate Driver for Improving Switching Performance of High-Power SiC MOSFET Modules

Featuring higher switching speed and lower losses, the silicon carbide mosfet s (SiC mosfet s) are widely used in higher power density and higher efficiency power electronic applications as a new solution. However, the increase of the switching speed induces oscillations, overshoots, electromagnetic interference (EMI), and even additional losses. In this paper, a novel active gate driver (AGD) for high-power SiC mosfet s is presented to fully utilize its potential of high-speed characteristic under different operation temperatures and load currents. The principle of the AGD is based on drive voltage decrement during the voltage and current slopes since high dV/dt and dI/dt are the source of the overshoots, oscillations, and EMI problems. In addition, the optimal drive voltage switching delay time has been analyzed and calculated considering a tradeoff between switching losses and switching stresses. Compared to conventional gate driver with fixed drive voltage, the proposed AGD has the capability of suppressing the overshoots, oscillations, and reducing losses without compromising the EMI. Finally, the switching performance of the AGD was experimentally verified on 1.2 kV/300 A and 1.7 kV/300 A SiC mosfet s in double pulse test under different operation temperatures and load currents. In addition, an EMI discussion and cost analysis were realized for AGD.