Conventional Flip-flop Research Articles

SEU Performance of RHBD Flip-Flops Using Guard Gates at 22-nm FDSOI Technology Node

Because of the isolation of transistors, fully-depleted silicon-on-insulator (FDSOI) technology nodes have shown better single-event upset (SEU) resilience compared with bulk technology nodes. Additional radiation-hardening-by-design (RHBD) techniques can further improve the SEU performance. In this paper, SEU performance of multiple RHBD flip-flop (FF) designs using the guard-gate circuit at a 22-nm FDSOI technology is presented, including a conventional FF, a guard-gate (GG) FF, a dual-feedback-recovery (DFR) FF, and a GG-Dual-Interconnected Storage Cell (DICE) FF. Irradiation results showed significant reductions in SEU cross-sections for hardened designs compared to the conventional design. Specifically, the conventional GG design demonstrates more than 100X improvement over a conventional FF design, while DFR and GG-DICE designs showed no upsets for all test conditions. Further analysis was carried out to explain the SEU performance differences between the GG and DFR FF designs, and it is noted that proper layout arrangement is critical for achieving ideal SEU mitigation in this FDSOI technology node.

Design of a Dual Change-Sensing 24T Flip-Flop in 65 nm CMOS Technology for Ultra Low-Power System Chips

In this paper, a flip-flop (FF) that minimizes the transition of internal nodes by using a dual change-sensing scheme is discussed. Further, in order to reduce power consumption, a new technique to eliminate short-circuit currents is described. The proposed dual change-sensing FF (DCSFF) composed of 24T (T: number of transistors) has the lowest dynamic power consumption among conventional FFs, independent of the data activity ratio. According to the measured results with a 65 nm CMOS process, the power consumption of DCSFF is reduced by 98% and 32%, when the data activity is close to 0% and 100%, respectively, compared to that of conventional transmission gate FF. Further, compared to that of change-sensing FF, the power consumption of DCSFF is reduced by 26% when the data activity is close to 100%.

High-Speed, Energy-Efficient Magnetic Nonvolatile Flip-Flop With Self-Adaptive Write Circuit Utilizing Voltage-Controlled Magnetic Anisotropy

Flip-flops (FFs) account for a very significant portion of the entire power consumption of VLSI circuits. Magnetic tunnel junctions (MTJs) can be combined with conventional FFs to achieve nonvolatility, almost unlimited write times, and higher energy efficiency. The mainstream MTJ switching mechanisms include spin-transfer torque (STT), spin-orbit torque (SOT), and voltage-controlled magnetic anisotropy (VCMA) effect, among them the first two mechanisms all facing the disadvantages of both large writing energy and writing latency. Instead, utilizing the VCMA effect to switch MTJ only needs a sub-nanosecond and has low energy consumption, which is more energy-efficient. In this article, first, a double-stage pre-charge sense amplifier (DPCSA) is proposed, reducing 53.9% of sensing delay compared with the conventional one. Second, based on DPCSA, a VCMA-MTJ-based multi-bit shared magnetic nonvolatile FF (MNV-FF) with a self-adaptive writing circuit is designed, achieving high speed and energy efficiency for backup and restore operations. Finally, by extending the MNV-FF, a magnetic nonvolatile register group (MNV-RG) with high area efficiency can be obtained. An SMIC 55 nm CMOS design kit and a VCMA-MTJ compact model described by Verilog-A language are used for hybrid simulation on the Cadence/Specter Platform. Simulation results in $0.7\times $ and $1.3\times $ of the improvements in data backup time and backup energy, respectively, compared with the efficient VCMA-MTJ-based MNV-FF. Two more improvements of $158.7\times $ and $19.6\times $ in data restore time and restore energy are also achieved in the same comparison.

A New Low Power Schema for Stream Processors Front-End with Power-Aware DA-Based FIR Filters by Investigation of Image Transitions Sparsity

Data stream processors and accelerators, due to the outstanding energy performance, run on hardware more than any time in modern designs. The general model for these processors comprises massive shift register arrays with the largest share in energy dissipation and processing elements (PE). In this paper, a new gated flip-flop is designed and utilized in shift register arrays, to decrease power consumption. Distributed arithmetic (DA) is an efficient method for calculating the inner product and FIR filters. DA-based FIR filter consists of two parts of shift register and PE array. Due to the significant share of power in shift register, in this paper, DA-based FIR filter is employed to show the improvement of the proposed gated flip-flop. Investigation of statistical properties of input in image processing applications, utilization of implicit clock gating, and multi-vdd techniques are three main approaches we used in this study to increase energy efficiency. It is shown that the transition density (TD) in 50% of static images of target databases is lower than 0.5. A set of random data with different TDs is generated, fed to the gated flip-flop in 180 nm technology, and the results show a 62–2% improvement in dynamic power consumption. Further optimization of 29–21% is achieved when the multi-vdd is applied on the wrapper circuit of the gated flip-flop. Likewise, using the proposed flip-flop in the shift register unit of the DA-based FIR filter has improved the power consumption by 15–40% compared to the conventional flip-flop.

Low power pulsed flip-flop with clock gating and conditional pulse enhancement

A clock system consumes above 25% of the total system power. Flip-flops (FFs) are widely used as the basic storage element in all kinds of digital structures. The use of pulse-triggered flip-flops (P-FFs) in digital design provides better performance than conventional flip-flop designs. This paper presents the design of a new power-efficient implicit pulse-triggered flip-flop suitable for low power applications. Two important features are embedded in this flip-flop architecture. Firstly, the enhancement in width and height of trigger pulses during specific conditions gives a solution for the longest discharging path problem in existing P-FFs. Secondly, the clock gating concept reduces unwanted switching activities at sleep/idle mode of operation and thereby reducing dynamic power consumption. The post-layout simulation results in cadence software based on CMOS 90 nm technology shows that the proposed design features less power dissipation and better power delay performance (PDP) when compared with conventional P-FFs. This paper also presents a comparative study on the performance of implicit and explicit pulse flip-flop designs. The maximum power saving of proposed design against conventional implicit and explicit design is up to 18.45% and 58.49%, respectively.

Low power pulsed flip-flop with clock gating and conditional pulse enhancement

A clock system consumes above 25% of the total system power. Flip-flops (FFs) are widely used as the basic storage element in all kinds of digital structures. The use of pulse-triggered flip-flops (P-FFs) in digital design provides better performance than conventional flip-flop designs. This paper presents the design of a new power-efficient implicit pulse-triggered flip-flop suitable for low power applications. Two important features are embedded in this flip-flop architecture. Firstly, the enhancement in width and height of trigger pulses during specific conditions gives a solution for the longest discharging path problem in existing P-FFs. Secondly, the clock gating concept reduces unwanted switching activities at sleep/idle mode of operation and thereby reducing dynamic power consumption. The post-layout simulation results in cadence software based on CMOS 90 nm technology shows that the proposed design features less power dissipation and better power delay performance (PDP) when compared with conventional P-FFs. This paper also presents a comparative study on the performance of implicit and explicit pulse flip-flop designs. The maximum power saving of proposed design against conventional implicit and explicit design is up to 18.45% and 58.49%, respectively.

Investigation of Buried-Well Potential Perturbation Effects on SEU in SOI DICE-Based Flip-Flop Under Proton Irradiation

The effects of buried-well potential perturbation under the buried-oxide (BOX) layer are studied in both a heavy-ion single event upset (SEU) test and a high-energy proton-SEU test of a silicon-on-insulator (SOI) dual interlocked storage cell (DICE)-based flip-flop. Their dependence on incident angle and back bias is discussed. We fabricated both DICE-based flip-flop and conventional flip-flop, which are designed as 80 000-stage shift-register chains. In a heavy-ion test, a considerable number of SEUs were observed at back bias exceeding 2.4 V, and a ten-times larger SEU-cross section was finally recorded at back bias of 3.0 V compared with the total active area of a DICE-based flip-flop cell. This marks the first case where DICE topology was found to be broken by buried-well potential perturbation on an SOI DICE-based flip-flop. In a proton test, one error was observed at back bias of 2.0 V. The SEU rate in the Van Allen belt at an altitude of 2300 km and an inclination of 90° was estimated as being once every 5 years.

A 12.6 mW, 573–2901 kS/s Reconfigurable Processor for Reconstruction of Compressively Sensed Physiological Signals

This article presents a reconfigurable processor based on the alternating direction method of multipliers (ADMM) algorithm for reconstructing compressively sensed physiological signals. The architecture is flexible to support physiological ExG [electrocardiography (ECG), electromyography (EMG), and electroencephalography (EEG)] signal with various signal dimensions (128, 256, 384, and 512). Data characteristics are utilized to substantially reduce the overall hardware complexity by up to 99%. A 16 $\times $ folded architecture achieves a 64% area-power product reduction compared with the unfolded one. A customized buffer is used for multi-word access, which reduces data latency by four times. It dissipates 75% less power with only 25% area when compared with the realization with conventional flip-flops. As a proof of concept, a reconfigurable processor for reconstructing ExG signals is presented. Fabricated in a 40-nm CMOS technology, the processor integrates 3.69-M gates in 3.23 mm2. The chip delivers a throughput of 573–2901 kSamples/s (kS/s) for ExG signals and dissipates less than 12.6 mW at 87 MHz from a 0.60-V supply. Compared with state-of-the-art designs, the chip achieves a 1.5-to-14 $\times $ higher throughput with 3.2-to-11 $\times $ less energy, given the performance specification [reconstruction signal-to-noise ratio (RSNR) ≥ 15 dB].

Fine-Grained Power Gating Using an MRAM-CMOS Non-Volatile Flip-Flop.

An area-efficient non-volatile flip flop (NVFF) is proposed. Two minimum-sized Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and two magnetic tunnel junction (MTJ) devices are added on top of a conventional D flip-flop for temporary storage during the power-down. An area overhead of the temporary storage is minimized by reusing a part of the D flip-flop and an energy overhead is reduced by a current-reuse technique. In addition, two optimization strategies of the use of the proposed NVFF are proposed: (1) A module-based placement in a design phase for minimizing the area overhead; and (2) a dynamic write pulse modulation at runtime for reducing the energy overhead. We evaluated the proposed NVFF circuit using a compact MTJ model targeting an implementation in a 10 nm technology node. Results indicate that area overhead is normalized to the conventional flip flop. Compared to the best previously known NVFFs, the proposed circuit succeeded in reducing the area by and the energy by . The proposed placement strategy of the NVFF shows an improvement of nearly a factor of 2–18 in terms of area and energy, and the pulse duration modulation provides a further energy reduction depending on fault tolerance of programs.

Design of implicit pulsed-dual edge triggering flip flop for low power and high speed clocking systems

The flip-flops are considered as major contributors to the power dissipation of the clocking system, which is made up of the clock provision network and storage elements (latches, flip-flops). The power- and delay-efficient new implicit-pulsed dual-edge triggering flip-flop circuit (IP-DETFF) is proposed with two latching stages by employing an implicit-pulse triggering, dual-edge clocking and reducing the number of clocked loads. This leads to the reduction of power consumption due to clock allocation tree (pclk-tree) and reduces the delay time. The dual-edge clocking technique is incorporated into this proposed design without an increment of the number of transistors and minimizes the operating frequency as half. This methodology is also employed in this proposed design to construct new latching part of the flip-flop circuit. The performance of proposed flip-flop is analyzed by simulating the circuit at 0.12[Formula: see text][Formula: see text]m CMOS (complementary metal oxide semiconductor) process technology. The simulation results show that the proposed design achieves power saving from 11.22% to 54.81%, improvement of speed from 67% to 71.50%, power-delay product (PDP) from 74.85% to 81.26 %, energy-delay product (EDP) from 87.86% to 92.4% and power-energy product (PEP) from 75.24% to 93.57% compared to the conventional flip-flops.

Effect of clock gating in conditional pulse enhancement flip-flop for low power applications

Flip-Flops (FFs) play a fundamental role in digital designs. A clock system consumes above 25% of total system power. The use of pulse-triggered flip-flops (P-FFs) in digital design provides better performance than conventional flip-flop designs. This paper presents the design of a new power-efficient implicit pulse-triggered flip-flop suitable for low power applications. This flip-flop architecture is embedded with two key features. Firstly, the enhancement in width and height of triggering pulses during specific conditions gives a solution for the longest discharging path problem in existing P-FFs. Secondly, the clock gating concept reduces unwanted switching activities at sleep/idle mode of operation and thereby reducing dynamic power consumption. The post-layout simulation results in cadence software based on CMOS 90-nm technology shows that the proposed design features less power dissipation and better power delay performance (PDP) when compared with conventional P-FFs. Its maximum power saving against conventional designs is up to 30.65% .

Improved low power implicit pulse triggered flip-flop with reduced power dissipation

In this paper, an improved implicit pulse triggered flip-flop is proposed based on conditional pulse enhancement scheme. The pass transistor logic AND gate creates a faster discharge path. Then a conditional pulse enhancement scheme is used in order to conditionally enhance the pulse only when required. This avoids unnecessary switching action in the flip-flop. Then in order to reduce the power dissipation further, the pseudo NMOS logic is replaced with a NAND gate structure. This reduces the static power consumption and as well as the switching power consumption. Thus results in an overall power saving. The results are obtained in 180 nm CMOS technology using mentor graphics. The results are compared with four conventional flip-flops and its power saving is improved.

HTD: A Light-Weight Holosymmetrical Transition Detector for Wide-Voltage-Range Variation Resilient ICs

To mitigate the excess timing margin in conventional digital integrated circuit design, resilient circuits were proposed. The current techniques however either have a large error-detecting register or have difficulty in wide-voltage-range (down to near-threshold) operation. In this paper, we propose a light-weight holosymmetrical transition detector (HTD) that can work reliably at near-threshold to normal VDD with fast response time. Combined with a conventional latch, the HTD-latch is used to replace the end point flip-flop for timing error prediction with an area overhead of only 9.5% over a conventional flip-flop. Besides, we optimize the speculation window and design an adaptive duty-cycle control mechanism to reduce the short-path padding overhead in a resilient circuit. In addition, with voltage scaling, we keep the system working at the point before the first failure by using local detection and global clock gating, which needs neither architectural circuit change nor complicated error recovery mechanism. We apply the above-mentioned three techniques on an eighth-order filter test chip in a 40-nm CMOS process. The measurement results demonstrate that the proposed HTD can work robustly at 0.474–1.1 V. With 4.37% area overhead in total, the proposed resilient technique improves performance by 179.31%/28.2% and energy efficiency by 45.6%/28.1% in a near- $V_{\mathrm {TH}}$ (0.474 V)/super- $V_{\mathrm {TH}}$ (1.1 V) operation, as compared with the baseline design. Therefore, our proposed HTD-based resilient technique can improve the energy efficiency of circuits by almost eliminating all the timing margins.

A 0.4-V, 0.138-fJ/Cycle Single-Phase-Clocking Redundant-Transition-Free 24T Flip-Flop With Change-Sensing Scheme in 40-nm CMOS

This paper presents an extremely low-voltage and low-power single-phase-clocking redundant-transition-free flip-flop (FF), named change-sensing FF (CSFF). By utilizing a local change-sensing scheme for eliminating redundant transitions of internal clocked nodes, CSFF does not consume any dynamic power when there is no data activity. Measurement results from a test chip fabricated in 40-nm CMOS technology show that CSFF saves up to 90% power dissipation at 5% data activity without additional transistors compared to the conventional transmission-gate FF (TGFF). CSFF consumes only 0.138 fJ/cycle, which is 84% lower than that of TGFF, at 0.4 V and 10% activity. In addition to the significant improvement in power and energy efficiencies, CSFF also enhances performance and minimum operating voltage. The test chip measurement demonstrates successful operations of CSFF down to 0.19 V and the delay improvement of 37% compared to TGFF in the supply voltage range of 0.4-1 V.

A novel low power flip-flop design using footless scheme

A low power true-single-phase clocking flip-flop (FF) design by using FootLess scheme named FLFF design targeting low VDD and low power operations is proposed. It is adapted from a recently presented FF design and achieves circuit simplification by using hybrid logic style. The optimization measure leads to a new design featuring better both power and speed performances. Based on the simulation results, the proposed design outperforms the conventional transmission gate flip-flop (TGFF) by 84% in energy. An 8-bit Johnson-counter consisting of the proposed FF design is developed and implemented. For the target 250 MHz working frequency, the proposed design achieves over 48.3% power saving with 14.6% area reducing.

Low Overhead Warning Flip-Flop Based on Charge Sharing for Timing Slack Monitoring

Timing error predictors have a strong potential to reduce the worst case timing margins by monitoring timing slack of a design. However, these timing error predictors incur substantial amount of silicon area and power which limit the overall benefits in the system level. This paper presents a low overhead warning flip-flop (FF), which predicts setup time violations. It consists of a delay buffer and a warning generator along with a conventional master-slave FF. Low overhead FF can be designed by exploiting the concept of charge sharing to implement the warning generator. As the warning generator requires only seven transistors to predict the timing violation, the proposed warning FF occupies 30% less area and consumes 27% less power compared to the state-of-the-art timing error predictors. A test chip is fabricated using the proposed FF in a 130-nm CMOS technology to verify the functionality of the proposed warning FF in dynamic voltage and frequency scaling applications. Measurement results from the test chip show that a performance improvement of 44% can be achieved at a supply voltage of 0.9 V by employing the proposed technique compared to the worst case design. For a typical chip, the power consumption can be reduced by 36% compared to the worst case design.

Low-Power Resonant Clocking Using Soft Error Robust Energy Recovery Flip-Flops

An energy recovery or resonant clocking scheme is very attractive for saving the clock power in nanoscale ASICs and systems-on-chips, which have increased functionality and die sizes. The technology scaling followed Moore’s law, that lowers node capacitance and supply voltage, making nanoscale integrated circuits more vulnerable to radiation-induced single event upsets (SEUs) or soft errors. In this work, we propose soft-error robust flip-flops (FFs) capable of working with a sinusoidal resonant clock to save the overall chip power. The proposed conditional-pass Quatro (CPQ) FF and true single phase clock energy recovery (TSPCER) FF are based on a unique soft error robust latch, which we refer to as a Quatro latch. The proposed C2-DICE FF is based on a dual interlocked cell (DICE) latch. In addition to the storage cell, each FF consists of a unique input-stage and a two-transistor, two-input output buffer. In each FF with a sinusoidal clock, the transfer unit passes the data to the Quatro and DICE latches. The latches store the data values at two storage nodes and two redundant nodes, the latter enabling recovery from a particle-induced transient with or without multiple-node charge sharing. Post-layout simulations in 65nm CMOS technology show that the FF exhibits as much as 82% lower power-delay product compared to recently reported soft error robust FFs. We implemented 1024 proposed FFs distributed in an H-tree clock network driven by a resonant clock-generator that generates a 1–5 GHz sinusoidal clock signal. The simulation results show a power reduction of 93% on the clock tree and total power saving of up to 74% as compared to the same implementation using the conventional square-wave clocking scheme and FFs.

Improved low power implicit pulse triggered flip-flop with reduced power dissipation

In this paper, an improved implicit pulse triggered flip-flop is proposed based on conditional pulse enhancement scheme. The pass transistor logic AND gate creates a faster discharge path. Then a conditional pulse enhancement scheme is used in order to conditionally enhance the pulse only when required. This avoids unnecessary switching action in the flip-flop. Then in order to reduce the power dissipation further, the pseudo NMOS logic is replaced with a NAND gate structure. This reduces the static power consumption and as well as the switching power consumption. Thus results in an overall power saving. The results are obtained in 180 nm CMOS technology using mentor graphics. The results are compared with four conventional flip-flops and its power saving is improved.

Metastability immune and area efficient error masking flip-flop for timing error resilient designs

Reducing the worst case timing guard bands is one of the major concerns in high performance designs with limited power budget in the advanced nano-scale technology nodes. In this work, an error masking flip-flop is proposed to reduce the worst case timing guard bands by detecting and correcting timing violations. It consists of a pulse generator, an error detector and a multiplexer along with a conventional flip-flop. Exploiting an intermediate multiplexer between master and slave latch of a conventional flip-flop, the erroneous output state of the flip-flop due to timing violations is corrected by providing direct data to slave latch. The proposed flip-flop occupies 16% less area compared to error masking flip-flops available in literature. A core level clock gating is employed for error recovery which shifts the rising edge of the clock by one period in case of a timing violation. ISCAS’89 benchmark circuits, a 32-bit pipelined adder and a 16-bit pipelined multiplier are implemented in 130nm technology, which use error masking flip-flop for dynamic voltage and frequency scaling (DVFS). It is shown that using error masking flip-flops with DVFS can either reduce power consumption up to 20% or improve the performance up to 32% in typical operating conditions compared to worst case design.

Single-Event Performance of Sense-Amplifier Based Flip-Flop Design in a 16-nm Bulk FinFET CMOS Process

The increasing need for high-speed logic circuits is causing the conventional flip-flop (FF) designs to migrate to differential FF designs. With the small magnitude of input voltages (and the resulting small noise margins) needed for proper operation, sense-amplifier based FF designs (SAFF) are susceptible to single-event effects (SEE). Single event upset (SEU) performance of high-speed SAFF designs is investigated in this paper for 16-nm bulk FinFET CMOS technology. SEU cross-sections for SAFF are evaluated over particle LET, temperature, and operating frequency. Results show significant increases in cross-sections as a function of frequency, but not so for temperature. Results presented in this work can guide designers to harden the SAFF that satisfies their specific circuit SEU error rate constraints.