Conventional FinFET Research Articles

Impact of source/drain lateral straggle on GIDL current of low SS NC-FinFET

ABSTRACT In this paper, the gate-induced drain leakage (GIDL) issue in negative capacitance (NC-FinFET) has been comprehensively addressed using Sentaurus 3-D TCAD simulations. Incorporation of ferroelectric (FE) materials in the gate stack of NC-FinFET increases with current by 12% compared to that of baseline FinFET. A steeper sub-threshold swing (SS) of 8 mV/dec is achieved at a FE-thickness of 5 nm at a lateral straggle; (σ) = 0 nm. GIDL behaviour with respect to the variation of source/drain σ and gate oxide thicknesses of NC-FinFET with and without the presence of the GateTunneling model is thoroughly investigated. Investigations demonstrate that in NC-FinFET, there are steeper energy band profiles near source/drain owing to coupling of fringing fields to the ferroelectric layer, which exhibits a larger and prior commencement of the longitudinal band to band tunnelling current compared to conventional FinFET. Moreover, the effect of variation of σ on various parameters viz. SS, capacitance and transconductance has also been investigated, which shows better results for lower σ values. At σ = 0 nm, drain-induced barrier lowering is −187.23 mV/V as compared to that of σ = 5 nm, which is −355.3 mV/V. Furthermore, we have also investigated drain current noise spectral density (SID) and gate voltage noise spectral density (SVG) with respect to fin width (WFIN) at the optimised σ value.

Performance assessment of InGaAs–SOI–FinFET for enhancing switching capability using high-k dielectric

In this work, a high-k In0.53Ga0.47As silicon-on-insulator FinFET (InGaAs–SOI–FinFET) is presented for high-switching and ultra-low power applications at 7 nm gate length. Indium Gallium Arsenide (InGaAs) is a compound semiconductor that has gained attention in the field of semiconductor devices, including FinFETs. The incorporation of InGaAs in proposed FinFETs introduces several advantages, making it an attractive material for certain applications. InGaAs–SOI–FinFET performance has been observed and found high electron mobility, improved On-Current performance (ION), drain current (IDS), transconductance (gm), energy bands, lower subthreshold swing (SS), electric field, surface potential, and better short-channel behaviour. All the results of InGaAs–SOI–FinFET have been simultaneously compared with SOI-FinFET and conventional FinFET (C-FinFET). Incorporating InGaAs in the channel with high-k gate material enhances the drain current by ⁓75% and ⁓77% in the proposed device compared to the other two counterparts. Owing to the higher drain current in the InGaAs–SOI–FinFET, other parameters have also been improved, which leads to higher performance applications.

Novel superjunction Fin-based NiO/β-Ga2O3 HJFET with additional surface drift region channels for record-high performance

—In this paper, a novel superjunction fin-based NiO/β-Ga2O3 heterojunction field-effect transistor (SJ Fin-HJFET) is proposed and studied by simulations. Compared with the conventional Ga2O3 SJ FinFET, Ga2O3 SJ Fin-HJFET can generate surface conduction channels instead of depletion zones near the p-n junction interface in the SJ drift region. The additional surface conduction channel significantly improves the specific on-resistance of the SJ Fin-HJFET (from 1.091 mΩ cm2 to 0.397 mΩ cm2, reduced by 63.6 %) and dramatically improves the Baliga figure of merit (BFOM, form 11.75 GW/cm2 to 32.28 GW/cm2) at the same breakdown voltage (3580 V). The effect of different conduction band offset (ΔEC) on the performance of the SJ Fin-HJFET is also investigated. The simulation results show that the on-resistance advantage of the SJ Fin-HJFET applies to a wide range of ΔEC, exhibiting strong applicability and stability. These results indicate that the SJ Fin-HJFET has record-high performance and promising application prospects.

N-DIBL optimization of NC-GAAFET NW for low power fast switching applications

Gate-all-around field effect transistors (GAAFETs), exhibit improved SCEs, are proposed to replace conventional FinFET in scaled nanodevices owing to excellent gate control. The voltage scaling concept is embodied in negative capacitance (NC) which provides same on current at reduced voltage. The proposed NC-GAAFET yields 5.31 times larger ION and IOFF is significantly reduced by ⁓105 orders, which is due NC effect, compared to baseline NW. SSavg for the NC-GAAFET is 33mV/dec which surpasses Boltzmann tyranny and manifests steep subthreshold behavior. Effect of FE thickness (tfe) variations on DIBL has been explored and found to be negative, which improves SCEs. The negative-DIBL for device has been found to be −20 mV/V at tfe = 6 nm. Furthermore, a CMOS inverter circuit employing the NC-GAAFET has been presented that provides an average propagation delay of 174 fS which is 47 % lesser as compared to that of baseline device. The NC-GAAFET NW findings fulfill the quest of low power fast switching device for digital applications.

A novel high-performance TG-based SRAM cell with 5 nm FinFET technology

In this study, we investigate the performance and reliability of a novel static random-access memory (SRAM) cell utilizing advanced 5 nm FinFET technology. Our research aims to address critical challenges in SRAM design by integrating transmission gates and power gated transistors. Through extensive simulations using the Cadence Virtuoso tool, we optimize the SRAM cell’s read and write paths, resulting in substantial improvements in both functionalities. Additionally, our study unveils temperature-dependent variations in the read current and write margin, emphasizing the influence of temperature on SRAM performance. Compared to conventional FinFET SRAM circuits of equivalent bit-cell area and read latency, our innovative design showcases remarkable improvements across various parameters. Specifically, we achieve a commendable increase of 6.16% in the write static noise margin (WSNM) and 5.86% in the hold static noise margin (HSNM). Moreover, our findings reveal a substantial boost in read stability, increasing from 14.75% to 18.35%. These advancements underscore the promising potential of our approach in paving the way for future innovations in high-performance memory architectures. By leveraging state-of-the-art technology and meticulous optimization techniques, our research sets a new standard for SRAM design, offering enhanced performance, reliability, and efficiency in memory systems.

Thermal management and switching performance of β-Ga2O3 vertical FinFET with diamond-gate structure

In this paper, a beta-phase gallium oxide (β-Ga2O3) vertical FinFET with diamond-gate has been studied by Silvaco-ATLAS simulation. The diamond-gate structure achieves adjustable pin (p-insulator-n) junction owing to the diamond-SiO2-Ga2O3 heterostructure. This design also enhances heat dissipation by virtue of the high thermal conductivity of the diamond. Compared to conventional FinFETs, the diamond-gate FinFET (DG-FinFET) reduces the static operating temperature rise by around 17.30%. Additionally, due to its greater heat dissipation capacity, DG-FinFETs provide a 5.84% increase in current density at 1 kA cm−2 current density level. The structural changes in the diamond-gate also result in a significant reduction in the gate-source capacitance (C GS). At 1 MHz operating frequency and the same gate voltage, DG-FinFETs have 69.29% less gate-source charge (Q GS), 70.80% less charge/discharge delay time, 73.70% less switching loss, and 57.15% less conduction loss. Overall, the simulation and analysis presented in this work indicate a promising advancement of the DG-FinFET structure in high-power and rapid switching applications.

Analysis of thermal stability in underlap and overlap DMG FinFETs including self-heating effects

This work investigates the impact of the self-heating effect (SHE) on SOI Dual-Material Gate (DMG) FinFETs with channel engineering including gate underlapped and overlapped structures. Both these structures are compared with conventional DMG FinFET to detect the possible effects of SHE on DC characteristics and thermal parameters. The drop rates of ON current (ION), Off-current (IOFF), Maximum transconductance (gm,max), ION/IOFF ratio, and Drain-induced barrier lowering (DIBL) are calculated to get the precise results. For extensive thermal reliability analysis, the two main distinguishing parameters lattice temperature and thermal resistance are also calculated and their dependency with gate/drain bias and operating temperature are also explored. Comparison between thin and thick BOX devices aimed at distinguishing possible effects of SHE on BOX thickness variation. The result shows that the SHE greatly improves ION/IOFF ratio by 220.8% in gate underlap structure due to large reduction in leakage current. Although lattice temperature is higher in gate overlap structure but thermal resistance decreases by 53.6 % due to its high ON current. Using high-k dielectric BOX materials, small improvement in device SHE characteristics is also accomplished.

Performance investigation of stacked-channel junctionless Tri-Gate FinFET 8T-SRAM cell

Junctionless FinFET devices are a substitute for conventional FinFET devices due to their short channel effects and easy manufacturing at sub 22 nm technology node. The manuscript presents an 8T-SRAM cell based on tri-gate junctionless FinFET technology. The FinFET device is designed with source/drain of Si material and the channel as a stack of Si − Si 0.75 Ge 0.25 − Si. The proposed SRAM cell structure consists of a CMOS inverter with stacked p-FinFETs, improving its performance in terms of noise margin and leakage power consumption. The manuscript investigates the variation of Static Noise Margin (SNM), leakage power dissipation and delay with supply voltage to analyze the sub-threshold operation of SRAM cell. The results reveal that the cascaded p-FinFETs minimize the leakage current owing to the stack effect, resulting in improved noise margin and lower leakage power. The stacked p-FinFET devices based SRAM cell achieves 1.11x read noise margin, 1.11x hold noise margin, −1.08x write noise margin and 57.1% less leakage power compared to conventional SRAM cell at 1.0 V. However, it exhibits more delay due to increased resistance and capacitance of the cascaded transistors. The process variation analysis is also performed to investigate the SNM distribution using monte-carlo simulation by taking 10,000 samples. The results indicate that the SRAM cell structures provide higher than 6σ yield at range of supply voltages.

TID response of hybrid FinFET with modified gate dielectric

The total ionizing dose response of hybrid FinFET with a modified gate stack (GS) is investigated and examined for the various ultra-thin body (UTB) layers and combination of gate oxide stacks. Incorporation of UTB layer to the conventional FinFET enhances the mechanical strength of the device. While being irradiated, conventional FinFET with UTB layer reduces the accumulation of trap charges to a certain level. Further, reduction of these charges can be achieved by using a high-k dielectric with UTB layer. This reduction in interface trap charges enhance the OFF-state performance while maintaines the positive threshold voltage of the device. The combination of UTB and GS in SOI-FinFET renders it more reliable and tolerant to ionizing dose.

Design of Smart Alu with Error Detection and Correction at Input Side

We are moving towards the era of scaling down of transistor size, short channel effects (SCEs) and errors are becoming major concern. NSFET is emerging transistors, which gives better SCEs performance compared to conventional MOSFET and FinFET transistors. In this paper, (7, 4) Hamming code was implemented at input side of ALU to prevent error which occur when the transistors size decreases (scale down). The efficiency of any system depends on the performance of internal components. If internal components satisfy the criteria of area, power and delay, the system will always be a efficient system, therefore in this paper the smart ALU was designed by making the internal components to satisfy criteria of area, power and delay. All internal components of ALU including (7, 4) Hamming code was designed by using MICROWIND 3.9 and DSCH 3.9 software and each component design was started from schematic diagram and moved up to automatic physical design by using Verilog code and including post layout simulation with spice netlist which contains parasitic parameters and finally area, power consumption, propagation delay including global delay analysis with RC information and operating frequency of each internal components of ALU was measured and compared with existing one and also Number of error detected and corrected was measured. Two kind of technology was used depending on their advantages (3nm technology for arithmetic design and 7nm technology for remain component design).

Design Considerations into Circuit Applications for Structurally Optimised FinFET

FinFETs have gained a lot of demand in the family of multigate FET devices in the recent years. In this view, this manuscript aims to design different FinFET architectures to observe the analog and circuit performance. A total of five structures namely Conventional FinFET, Lightly doped S/D, Underlap FinFET, Single-k spacer, and Dual-k spacer FinFET has been designed and performance has been analysed. The best performance is obtained for dual-k spacer FinFET. Moreover, the dimensional variations such as gate length (Lg), fin width (Wfin) and fin height (Hfin) for the duak-k spacer FinFET is performed and it is found that lowering the Lg and Wfin, and increasing the Hfin would be a better option in order to enhance the device performance. Furthermore, at the optimized device dimensions the circuit analysis for inverter and single stage common source amplifier is performed. The gain for the designed single stage common stage amplifier is noticed to be 1.8155.

Quality factor and digital inverter performance in gate underlap and overlap DMG FinFETs

This paper presents a comparative 3D simulation study of Quality factor among Gate Underlap and Overlap techniques in both Si and Ge Dual Material Gate (DMG) FinFETs using the Sentaurus TCAD tool. The results of both the techniques are carefully examined and compared with Conventional DMG FinFET to analyze the performances of these devices. The effect of gate overlap/underlap techniques on threshold voltage (Vth), ION/IOFF ratio, drain induced barrier lowering (DIBL), transconductance (gm), subthreshold swing (SS), and Quality factor (Q) are investigated. It is found that Ge DMG FinFETs have higher gm and quality factor values as compared to Si DMG FinFETs. The prospects of these techniques in low-power digital applications have been performed by implementing complementary Si DMG FinFET based inverter circuit. We have extracted the average delay and noise margin, where the overlap structure performs better such as high current gain and no overshoot/undershoot peaks in the transient characteristics.

Junctionless-accumulation-mode stacked gate GAA FinFET with dual-k spacer for reliable RFIC design

This study investigates how incorporating a dual-k spacer (SiO2 + HfO2) affects the RFIC design feasibility of a junctionless-accumulation-mode (JAM) stacked-gate (GS) gate-all-around (GAA) FinFET in the sub-10 nm range. The proposed device is compared with a conventional FinFET and those without a spacer, air, and a single-k spacer (SiO2). At a low voltage power supply, fringing field effects raise the proposed device's on-current by 35.34% and reduce the off-current by more than 76 times compared to conventional FinFET, thereby improving electron velocity, energy band profiles, transconductance, device efficiency, etc. Thus, the proposed device is well-suited for high-performance CMOS circuits. Further investigation shows that integrating a dual-k spacer reduces the output conductance, which boosts the intrinsic gain and early voltage by five times the value recorded for conventional FinFET. Although the cut-off frequency drops by 15.98%, the GTFP and GFP soar by 475.67% and 352.25%, respectively. Consequently, JAM-GS-GAA FinFET with dual-k spacer is an encouraging device for low-power RFIC circuits.

Engineering negative differential resistance in negative capacitance Quad-FinFET

In this work, a systematically analysis of the Negative Capacitance (NC) Quad-FinFET structure is carried out where we determine the optimal FE layer thickness that enables hysteresis-free transfer characteristics. However, negative differential resistance (NDR) is introduced along with the increased FE-layer thickness, which is not desirable for application in analogcircuits. Through the implementation of an asymmetric drain length extension and a high-k Si3N4 spacer, negative differential resistance (NDR) can be mitigated. In addition, the relatively poor analog performance generally seen in conventional FinFET structures are overcome in the drain engineered NC Quad-FinFET structure with gate spacer resulting in significant improvement in performance parameters such as transconductance, output conductance and intrinsic gain. The integration of NC Quad-FinFET as a digital inverter is carried out where the circuit propagation delay is decreased by 27.65% with drain length extension and inclusion of Si3N4 spacer. Thus, through these device optimization techniques, the NC Quad-FinFET structure shows significant improvement in both analog and digital device performance parameters.

Performance estimation of non-hysteretic negative capacitance FinFET based SRAM

In this paper, a detailed evaluation of negative capacitance FinFET (NC-FinFET) based volatile static random access memory (6T-NCSRAM) is carried out by utilizing L-K equation for ferroelectric and calibrated BSIM-CMG model with 14 nm conventional FinFET to form NC-FinFET. Static and dynamic behavior of NC-FinFETs is explored and evaluated at different ferroelectric thickness. At supply voltage scaling, important SRAM performance metrics such as stability at different operation condition (hold, read and write mode) and standby leakage power were evaluated. When compared to traditional FinFET based SRAM, 6T-NCSRAM exhibits distinct behavior during low and high supply voltages. Moreover, the effect of wordline (WL) voltage pulse variation on 6T-NCSRAM is captured and minimum RC multiplier of 2RC is found to avoid functional failure of 6T-NCSRAM.

Design and implementation of 10T-SRAM cell using Carbon Nano Tube Field Effect Transistor

SRAM is a key component in many VLSI circuits for efficient storage data. Various researches have been performed on implementation of SRAM using Conventional CMOS, FinFET and GNRFET technologies. But, these methodologies generating the more number of faults with high power and delay consumption, tosolve this problem proposed10T SRAM cell is implemented with the CNTFET respectively. Present research involving CNTFET SRAM deals with leakage analysis and dealt with the dual hilarity characteristics. Fault introduction and analysis of faults were limited with CMOS SRAM. The detection algorithms and circuits possess limitations in terms of detecting the current at nanoscales and restricted with CMOS SRAM. These limitations made us to pursue the research in these areas to bring novel ideas. The performance metrics evaluated and experimental analysis is made and it helps us to choose between various SRAMS. The simulation results shows that the proposed 10T SRAM consumes less delay and power compared to the 7T SRAM cell.

Compressive Strained Si1-XGex Channel for High Performance Gate-All-Around Nanosheet Transistors

As scaling of conventional FinFET architecture to achieve target transistor density and performance becomes more complex and difficult, it is essential to attain a next generation transistor architecture. Horizontal Gate-All-Around (hGAA) nanosheet (NS) devices have attracted attention as a candidate to replace FinFETs at the 5nm technology node and beyond due to their excellent electrostatics and short channel control. Compared to scaled FinFET, stacked GAA NS offers circuit performance improvements with increased effective width per active footprint while also enabling gate length scaling. Exploring performance improvement techniques, such as channel strain engineering, is important for next generation CMOS technologies. It is difficult, however, to effectively induce strain into the channel region using source/drain stressors in scaled GAA NS structures due to reduction of the stressor (embedded SiGe in source/drain region) volume as transistor dimension shrinks. In addition, strain relaxation of source/drain stressors caused by introduction of crystalline defects decreases effectiveness to induce strain into the channel region. This is more pronounced by the fact that achieving superior epitaxial growth is more difficult on the GAA NS device structure due to the presence of inner spacer dielectric. Therefore, we proposed a stacked GAA NS pFET device with compressively strained SiGe channel. The SiGe channel NS devices were fabricated using Si NS channel trimming by selective isotropic dry etch and selective SiGe epitaxial growth techniques after the Si NS channel release (Fig. 1). This is the preferable scheme in terms of strain retention in the SiGe channel NS region since there are no patterning processes that cause strain relaxation during downstream processing.To investigate the device characteristics of SiGe NS devices, we fabricated strained Si1-xGex (x = 0.2, 0.25, 0.3, and 0.35) channel NS pFET and investigated the crystallinity and strain in the channel region. Fig. 2 contains cross-sectional TEM images across the gate after Si0.7Ge0.3 channel formation. We observed no visible crystalline defects in the 4 nm-thick Si0.7Ge0.3 layer grown on the 2 nm-thick trimmed Si NS, indicating superior crystallinity of Si0.7Ge0.3 layer. To investigate strain in the nanoscale strained SiGe NS channel structures, Precession Electron Diffraction (PED) characterization was performed to evaluate lattice deformation of the stacked SiGe NS channel with 4 nm-thick Si0.7Ge0.3 epitaxial growth. Lattice deformation values are defined as the difference between in-plane lattice constants and the Si lattice constant, normalized by the Si lattice constant. Fig. 3 shows in-plane lattice deformation contour maps in the region of the stacked SiGe NS channel obtained from both X-cut (across the gate) and Y-cut (along the gate) for the SiGe NS structure with sheet width of 20 nm. The in-plane lattice deformation values were extracted from the middle of the SiGe NS channel as shown in Fig. 4. Preservation of half the amount of strain along the channel direction ([110]) was confirmed whereas strain along the NS width direction ([1-10]) was found to be almost fully relaxed due to elastic relaxation. This results in the Si0.7Ge0.3 channel being uniaxially stressed. The compressive stress along the channel direction estimated from the [110] lattice deformation is ~1 GPa.Normalized hole mobility in the representative Si1-xGex channel NS pFET as a function of inversion carrier density (Ninv) is shown in Fig. 5. The hole mobility of Si1-xGex channel (x = 0.35) with Si cap is almost 100% higher than that of Si NS channel. The mobility benefit of Si1-xGex channel is attributed to reduced effective hole mass along the transport direction caused by a high compressive strain in the Si1-xGex channel.The technique demonstrated in this study for forming compressively strained SiGe channel NS has great potential to improve pFET device performance for next generation of CMOS logic in GAA Nanosheet technology. Figure 1

Vertical Gate-All-Around Device Architecture to Improve the Device Performance for Sub-5-nm Technology.

In this work, we propose a vertical gate-all-around device architecture (GAA-FinFET) with the aim of simultaneously improving device performance as well as addressing the short channel effect (SCE). The GAA-FinFET was built using the technology computer-aided design (TCAD) simulation tool, and then, its electrical characteristics were quantitatively evaluated. The electrical characteristics of the GAA-FinFET were compared to those of conventional FinFET and nano-sheet FET (NSFET) at 7 nm or 5 nm nodes. When comparing the GAA-FinFET against the FinFET, it achieved not only better SCE characteristics, but also higher on-state drive current due to its gate-all-around device structure. This helps to improve the ratio of effective drive current to off-state leakage current (i.e., Ieff/Ioff) by ~30%, resulting in an improvement in DC device performance by ~10%. When comparing the GAA-FinFET against the NSFET, it exhibited SCE characteristics that were comparable or superior thanks to its improved sub-channel leakage suppression. It turned out that the proposed GAA-FinFET (compared to conventional FinFET at the 7 nm or 5 nm nodes, or even beyond) is an attractive option for improving device performance in terms of SCE and series resistance. Furthermore, it is expected that the device structure of GAA-FinFET is very similar to that of conventional FinFET, resulting in further improvement to its electrical characteristics as a result of its gate-all-around device structure without significant modification with respect to the processing steps for conventional FinFET.

Comprehensive Power Gain Assessment of GaN-SOI-FinFET for Improved RF/Wireless Performance Using TCAD.

In this work, we present a radio frequency (RF) assessment of the nanoscale gallium nitride-silicon-on-insulator fin field-effect transistor (GaN-SOI-FinFET). All the performances of the device were compared with GaN-FinFET and conventional FinFET (Conv. FinFET) simultaneously. All the results show that the power gains significantly improved in terms of Gma, Gms, Stern stability factor (SS), GMT, and intrinsic delay in comparison with conventional FinFET. Current gain and unilateral power gain were also evaluated for the extraction of fT (cut-off frequency) and fMAX, respectively. fT and fMAX were enhanced by 88.8% and 94.6%, respectively. This analysis was performed at several THz frequencies. Further, the parametric assessment was also performed in terms of gate length and oxide thickness to find the optimized value of gate length and oxide thickness. The implementation of GaN in the channel reduces the parasitic capacitance and paves the way for high-performance RF applications.

On the design of p-channel step-FinFET at sub-10nm node: A parametric analysis

This paper presents a three dimensional (3-D) statistical simulation study of a 7 nm technology node SOI p-channel step-FinFET and compares with that of a conventional FinFET (c-FinFET). For the first time we have investigated the impact of various dimensional parameters like Gate Length (LG), Fin width (Wfin1 and Wfin2, Wfin = fixed), Fin height (Hfin1 and Hfin2, Hfin = fixed) and Fin-width ratio on the performance of c-FinFET and step-FinFET devices. These FinFET structures have been designed and simulated in Cogenda Visual TCAD under certain boundary conditions and the performance has been analyzed. The electrical parameters such as ON-current (ION), OFF-current (IOFF), Sub-threshold Swing (SS), Drain Induced Barrier Lowering (DIBL), threshold voltage (Vt) roll-off, Transconductance (gm) and Transconductance Generation Factor (TGF) are extracted. It is observed that short channel effects (SCEs) can be controlled by reducing Wfin1, decreasing major fin height (Hfin1) and increasing Gate length (LG) (14 nm to 20 nm). It is noticed that there is a significant improvement in ION/IOFF ratio from 1.01 × 104 to 1.41 × 105 with respect to increased channel length, SS of 76.68 mV/decade to 67.8 mV/decade and excellent DIBL of 55 mV/V in c-FinFET. For the proposed step-FinFET at LG = 16 nm there is improved DIBL of 85 mV/V compared to the c-FinFET, which can be further improved up to 64.63 mV/V by decreasing the Hfin1/Hfin2 ratio (4 to 0.25). The parametric analysis concludes that step-FinFET is more susceptible to SCEs in terms of DIBL, Vt roll-off as compared to the c-FinFET. This work considers LG = 16 nm for analysing the dimensional variation effect on both the devices. In contrast c-FinFET is more preferable than the proposed device at lower technology nodes.