Conventional CMOS Circuits Research Articles

DFT with Universal Test Set for All Missing Gate Faults in Reversible Circuits

The design of reversible logic circuits has received considerable attention in recent times for their potential use in implementing quantum computers. A fault model, namely, the Missing-Gate Fault (MGF) model, has been found to be more suitable for modeling defects in quantum circuits as compared to the classical fault models used for testing conventional CMOS circuits. In this paper, we propose two design-for-testability techniques with universal test set to detect MGFs in a reversible circuit. In these techniques, an [Formula: see text] reversible circuit implemented with [Formula: see text]-CNOT gates is transformed to a testable design with addition of two extra inputs lines and some additional gates, which uses a universal test set of size [Formula: see text] to detect the MGFs. The proposed DFT techniques are compared with earlier works and it has been shown that these techniques outperform the earlier techniques with respect to quantum cost overhead and percentage detection of the different MGFs.

Performance Comparison of the Conventional CMOS and MTCMOS Digital Circuits and Their Simulation

This paper focuses on the design of the conventional CMOS digital circuits and the Multi-Threshold CMOS (MTCMOS) digital circuits, which perform the specific Boolean logic function, as well as the comparison between these designing techniques by their functionality and power consummation (dissipation). The leakage of currents in integrated circuits based on CMOS logic becomes quite significant when the complementary MOS transistors are the small-device geometries (small dimensions), and this effect imposes alternative techniques that enable the designing of CMOS digital circuits with low-power dissipation, even in standby mode. One of these techniques is the design of the CMOS digital circuits with multi-threshold voltage (MTCMOS), which enables the reduction of the leakage power dissipation, as a part of the overall power dissipation in CMOS logic. Two CMOS digital circuits are designed (2-input XNOR CMOS gate and the other one is the CMOS gate that performs a complex Boolean function) based on conventional CMOS technique and multi-threshold voltage CMOS technique, and their functionality and calculation of the average overall power dissipation are tested using the Computer-Aided Design (CAD). The methodology used to achieve low power dissipation in CMOS digital circuits (MTCMOS) will be an efficient method for reducing the overall dissipation, while the high speed performance will be maintained.

Design Automation of Superconductive Digital Circuits: A review

Electronic Design Automation (EDA) is essential for the design of large-scale microelectronic systems. In this article, EDA methodologies, techniques, and algorithms used to develop superconductive computing systems are reviewed. The semicustom standard cell-based design flow, common in conventional CMOS circuits, is widely adopted in modern superconductive digital circuits. Differences and issues in CAD flows as compared to CMOS design methodologies are highlighted. The most common stages of these design flows, from high-level simulation to physical layout, are described. These stages are grouped into three areas: simulation/modeling, synthesis/place and route, and verification. Modern approaches and tools for superconductive circuits are reviewed for each of these areas.

Analysis of circuit performance of Ge-Si hetero structure TFET based on analytical model

PurposeHigh packaging density in the present VLSI era builds an acute power crisis, which limits the use of MOSFET device as a constituent block in CMOS technology. This leads researchers in looking for alternative devices, which can replace the MOSFET in CMOS VLSI logic design. In a quest for alternative devices, tunnel field effect transistor emerged as a potential alternative in recent times. The purpose of this study is to enhance the performances of the proposed device structure and make it compatible with circuit implementation. Finally, the performances of that circuit are compared with CMOS circuit and a comparative study is made to find the superiority of the proposed circuit with respect to conventional CMOS circuit.Design/methodology/approachSilicon–germanium heterostructure is currently one of the most promising architectures for semiconductor devices such as tunnel field effect transistor. Analytical modeling is computed and programmed with MATLAB software. Two-dimensional device simulation is performed by using Silvaco TCAD (ATLAS). The modeled results are validated through the ATLAS simulation data. Therefore, an inverter circuit is implemented with the proposed device. The circuit is simulated with the Tanner EDA tool to evaluate its performances.FindingsThe proposed optimized device geometry delivers exceptionally low OFF current (order of 10^−18 A/um), fairly high ON current (5x10^−5 A/um) and a steep subthreshold slope (20 mV/decade) followed by excellent ON–OFF current ratio (order of 10^13) compared to the similar kind of heterostructures. With a very low threshold voltage, even lesser than 0.1 V, the proposed device emerged as a good replacement of MOSFET in CMOS-like digital circuits. Hence, the device is implemented to construct a resistive inverter to study the circuit performances. The resistive inverter circuit is compared with a resistive CMOS inverter circuit. Both the circuit performances are analyzed and compared in terms of power dissipation, propagation delay and power-delay product. The outcomes of the experiments prove that the performance matrices of heterojunction Tunnel FET (HTFET)-based inverter are way ahead of that of CMOS-based inverter.Originality/valueGermanium–silicon HTFET with stack gate oxide is analytically modeled and optimized in terms of performance matrices. The device performances are appreciable in comparison with the device structures published in contemporary literature. CMOS-like resistive inverter circuit, implemented with this proposed device, performs well and outruns the circuit performances of the conventional CMOS circuit at 45-nm technological node.

Introduction to spin wave computing

This paper provides a tutorial overview over recent vigorous efforts to develop computing systems based on spin waves instead of charges and voltages. Spin-wave computing can be considered a subfield of spintronics, which uses magnetic excitations for computation and memory applications. The Tutorial combines backgrounds in spin-wave and device physics as well as circuit engineering to create synergies between the physics and electrical engineering communities to advance the field toward practical spin-wave circuits. After an introduction to magnetic interactions and spin-wave physics, the basic aspects of spin-wave computing and individual spin-wave devices are reviewed. The focus is on spin-wave majority gates as they are the most prominently pursued device concept. Subsequently, we discuss the current status and the challenges to combine spin-wave gates and obtain circuits and ultimately computing systems, considering essential aspects such as gate interconnection, logic level restoration, input–output consistency, and fan-out achievement. We argue that spin-wave circuits need to be embedded in conventional complementary metal–oxide–semiconductor (CMOS) circuits to obtain complete functional hybrid computing systems. The state of the art of benchmarking such hybrid spin-wave–CMOS systems is reviewed, and the current challenges to realize such systems are discussed. The benchmark indicates that hybrid spin-wave–CMOS systems promise ultralow-power operation and may ultimately outperform conventional CMOS circuits in terms of the power-delay-area product. Current challenges to achieve this goal include low-power signal restoration in spin-wave circuits as well as efficient spin-wave transducers.

Wideband High-Resolution Frequency-to-Resistance Converter Based on Nonhomogeneous Magnetic-State Transitions

By harnessing the rich dynamics associated with nonhomogeneous magnetization configurations in confined nanostructures, the free layer of a magnetic tunnel junction (MTJ) can be forced, via a localized magnetic field, to transition between two magnetic states: the quasi-uniform and vortex states. Here, we demonstrate that such transitions can be driven back and forth to a dynamic equilibrium by exciting a MTJ with ac magnetic fields close to the resonant modes of the magnetic vortex. The frequency dependence of the dynamic-state transitions leads to a proposal for an alternative type of broadband analogue frequency-to-resistance converter (FRC). In this report, two quasilinear bands of the FRC are demonstrated: a relatively lower frequency converter operating between 200 and 350 MHz with 250-kHz resolution (\ensuremath{\sim}500 channels) and a higher frequency converter operating between 2.5 and 6 GHz with a 2.5-MHz resolution (\ensuremath{\sim}800 channels). The fact that a single CMOS-compatible nanoscale device can perform such a complex function over a multitude of frequency bands, with high-frequency resolution relative to that of conventional CMOS circuits, can enable the next generation of wireless communication circuit topologies.

An advanced adiabatic logic using Gate Overlap Tunnel FET (GOTFET) devices for ultra-low power VLSI sensor applications

Adiabatic circuits are ideally suited for implementing RFID tags and biomedical sensors due to their ultra-low power requirements. This paper presents a novel Gate Overlap Tunnel FET (GOTFET) based Advanced Adiabatic Logic which consumes upto 67% lower power than the equivalent CMOS based Symmetric Pass Gate Adiabatic Logic (SPGAL) which is the most power efficient adiabatic topology reported in recent literature. The basic building blocks of the proposed GOTFET Adiabatic Logic (GOTAL) circuits are the innovative Complementary GOTFETs (CGOT) which have twice the on state currents $$I_{on}$$ and one order lower off state currents $$I_{off}$$ than the corresponding MOSFETs having same width at the same technology node. In addition to the novel devices, the novelty in the proposed design is the usage of specially engineered low threshold voltage $$V_{t}$$ GOTFETs for minimizing non-adiabatic losses and completely avoiding the unnecessary complexity involving the generation of discharge pulse in the resetting clock circuit. Adiabatic inverter, NAND and NOR gates implemented using the proposed GOTAL circuits consume up to two orders (97%) lower power than the corresponding conventional static CMOS circuits at the same frequencies of operation under the same capacitive loads. Although adiabatic circuits are usually designed for low frequency operation, GOTAL circuits may also be used at higher frequencies owing to the improved frequency response of the CGOT devices.

Boolean Difference Technique for Detecting All Missing Gate and Stuck-at Faults in Reversible Circuits

Quantum reversible circuit is a new emerging technology attracting the researchers. A reversible circuit is composed of reversible gates. One example of reversible gate is Toffoli gate. A Toffoli gate (also known as [Formula: see text]-CNOT) has two components — the control and the target. Initially, stuck-at fault and other fault models were used for modeling defects in quantum reversible circuits. Later, a new fault model known as missing gate fault model was introduced, which is more effective in capturing the errors in quantum reversible circuit. Boolean Difference is already a known technique to detect stuck-at faults in conventional CMOS circuit. In this paper, Boolean Difference method is applied to derive the test set for detecting each stuck-at fault and missing gate fault in a reversible circuit. Then an optimization algorithm is used to derive an optimal test set, which will detect all possible faults in a circuit. The method is valid also for other fault models.

A Fast Logic Mapping Algorithm for Multiple-Type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays

Unlike conventional CMOS circuits, nano-crossbar arrays have considerably high defect rates. Multiple-type defects randomly occur both on crosspoint switches and wires that substantially complicates the design phase of the circuits with an elimination of systematic design choices. In order to overcome this problem, a logic mapping methodology is presented in this paper. A fast heuristic algorithm using pre-mapping logic morphing, defect oriented adaptive sorting, matching with Hadamard multiplication, and backtracking is introduced. The proposed algorithm covers both crosspoint defects including stuck-open and stuck-closed types and wire defects including bridging and broken types. Effects of stuck-closed defects, mostly disregarded in the literature, are studied in depth. In simulations, an industrial benchmark suit is used for obtaining runtime and success rate values of the proposed algorithm in comparison with those of the existing algorithms in the literature. A relative accuracy evaluation is also given in comparison with exact mapping techniques. Finally, the steps of the algorithm that are based on pre-mapping and heuristic matching techniques, are separately justified with experimental results.

A CMOS dynamic random access architecture for radio-frequency readout of quantum devices

Quantum computing technology is maturing at a relentless pace, yet individual quantum bits are wired one by one. As quantum processors become more complex, they require efficient interfaces to deliver signals for control and readout while keeping the number of inputs manageable. Digital electronics offers solutions to the scaling challenge by leveraging established industrial infrastructure and applying it to integrate silicon-based quantum devices with conventional CMOS circuits. Here, we combine both technologies at milikelvin temperatures and demonstrate the building blocks of a dynamic random access architecture for efficient readout of complex quantum circuits. Our circuit is divided into cells, each containing a CMOS quantum dot (QD) and a field-effect transistor that enables selective readout of the QD, as well as charge storage on the QD gate similar to 1T-1C DRAM technology. We show dynamic readout of two cells by interfacing them with a single radio-frequency resonator. Our results demonstrate a path to reducing the number of input lines per qubit and enable addressing of large-scale device arrays.

Emission and propagation of 1D and 2D spin waves with nanoscale wavelengths in anisotropic spin textures.

Spin waves offer intriguing perspectives for computing and signal processing, because their damping can be lower than the ohmic losses in conventional complementary metal-oxide-semiconductor (CMOS) circuits. Magnetic domain walls show considerable potential as magnonic waveguides for on-chip control of the spatial extent and propagation of spin waves. However, low-loss guidance of spin waves with nanoscale wavelengths and around angled tracks remains to be shown. Here, we demonstrate spin wave control using natural anisotropic features of magnetic order in an interlayer exchange-coupled ferromagnetic bilayer. We employ scanning transmission X-ray microscopy to image the generation of spin waves and their propagation across distances exceeding multiples of the wavelength. Spin waves propagate in extended planar geometries as well as along straight or curved one-dimensional domain walls. We observe wavelengths between 1 μm and 150 nm, with excitation frequencies ranging from 250 MHz to 3 GHz. Our results show routes towards the practical implementation of magnonic waveguides in the form of domain walls in future spin wave logic and computational circuits.

Overhead Requirements for Stateful Memristor Logic

Memristors are being explored as a potential technology to replace CMOS for logic-in-memory systems that exploit the memristive non-volatility. Memristors are two-terminal, non-volatile device that exhibit a variable resistance that is dependent on the applied voltage history of the device, providing the capability to store and process information within the same structure. The ability of memristors to perform logic has been previously demonstrated, but previous analyses of memristor logic efficiency have not included the overhead CMOS circuitry that is required to control memristor logic operations. In this paper, the required overhead CMOS circuitry for implementing logic with memristors is evaluated for standard logic gates and a one-bit full adder to enable an analysis of the overall system efficiency. The results show that the number of CMOS devices in the overhead circuitry can be upwards of 50 times that of a conventional CMOS implementation, and that the power-delay product of the memristor logic with overhead circuitry is roughly one billion times greater than for conventional CMOS circuits. These results enable the conclusion that the overhead circuit requirements for stateful memristor logic threaten to negate any efficiency improvements that are achieved by the memristors themselves.

Design and Analysis of Energy Efficient Domino Logic Architectures with Single Electron Transistors in Pull Down Network and Keeper Topology

Nanotechnology and VLSI goes hand in hand. Modernization of electronics and communication systems has demanded for compactness of the devices with low power and high speed. Conventionally CMOS logic is preferred due to its low power and its high speed benefits. Researches demand a new logic style that can effectively replace conventional CMOS. Many styles including Domino logic are already gaining attention in this regard. The proposed work introduces Single Electron Transistors (SET) instead of NMOS in Pull Down Network and Keeper transistor of Domino Logic. As SETs are predominant in Nanotechnology, when employed in domino logic circuits as a fusion with normal MOS transistors will contribute effectively in terms of area, power and delay. The parameters are estimated with Cadence 45nm (SET- Spice Model) technology. The proposed domino logic architectures come up with an average of 68% energy efficiency when compared with conventional CMOS circuit and its Domino logic predecessors.

Exploiting Reversible Computing for Latent-Fault-Free Error Detecting/Correcting CMOS Circuits

Unlike conventional CMOS circuits, reversible circuits do not have latent faults, so faults occurring in internal circuit nodes always result in an error at the output. This is a unique feature for online or concurrent fault tolerance and the main motivation of this paper with an aim of achieving highly efficient fault-tolerant CMOS logic circuits. For this purpose, we first implement fault-tolerant reversible circuits. We develop two techniques to make a reversible circuit fault-tolerant by using multiple-control Toffoli gates. The first technique is based on single parity preserving and offers error detection for odd number of errors at the output. The second technique is constructed on Hamming codes, which results in circuits detecting any number of errors unless the number of errors at the output is the order of $d$ or correcting $(d-1)/2$ bit errors, where $d$ is the minimum Hamming distance between any pair of bit patterns. We select $d=3$ in this paper. We also claim that 100% error detection is possible with conservative reversible gates, such as a Fredkin gate. For this purpose, we develop a greedy synthesis algorithm that implements an arbitrary reversible function with multiple-control Fredkin gates. As the next step, we utilize the proposed reversible circuits with conventional CMOS gates. This certainly approves the practical use of the proposed techniques. The effectiveness of our techniques is demonstrated on benchmark circuits, implemented by both reversible and CMOS gates, in terms of fault tolerance performances and area costs. Comparisons with the related studies in the literature as well as with dual-modular redundancy and triple-modular redundancy-based circuits clearly favor the proposed designs.

A Minimum Hamming Distance Search Associative Memory Using Neuron CMOS Inverters

SUMMARYRecently, high‐speed searching for the most similar reference data out of the database is needed for data compression, image recognition, network control, and others. However, it takes much time to search for data with software, or hardware using conventional memory. Associative memory has been developed as a high‐speed searching device. In this paper, we propose a minimum Hamming distance search associative memory using neuron CMOS inverters. The proposed associative memory is less affected by initial charge and a change of threshold voltage of neuron MOS transistors than conventional neuron CMOS circuits. The proposed circuit also makes searching speed higher by using fully parallel processing. We confirmed that the proposed circuit can be realized expected results by simulation, and experiment using test chip.

High‐performance engineered gate transistor‐based compact digital circuits

A novel method for designing and realising compact digital circuits by engineering MOSFET gate electrode is proposed. The novelty is the use of gate engineered single devices in the pull-up (PU) and pull-down (PD) paths of a static CMOS gate instead of multiple transistors as used in conventional CMOS implementations of circuits. Herein, two input NAND, NOR, and exclusive-OR (XOR) gates employing the proposed gate engineering concept are designed and simulated. Engineered gate N-type MOS and P-type MOS are used for PD and pull-up circuits, respectively. Since only two devices are used for a complete circuit: one in PU network and other in PD network; therefore, area and power of the proposed circuits get reduced significantly in comparison with the conventional static CMOS circuits. Mixed mode simulations have shown that the proposed technique realises NAND, NOR and XOR operations perfectly and it can be extended to realise other combinational and sequential circuits easily.

A Fault Tolerant Voter Circuit for Triple Modular Redundant System

Defect rate in Nanoelectronics is much higher than conventional CMOS circuits. Hardware redundancy can be a suitable solution for fault tolerance in nano level. A voter circuit is a part of a redundancy based fault tolerant system that enables a system to continue operating properly in the event of one or more faults within its components. Robustness of the voter circuit defines the reliability of the fault tolerant system. This paper provides simulation results and analysis of a fault tolerant voter circuit. In a Triple Modular Redundant (TMR) system, the robustness of the voter circuit has been improved. For this purpose, redundancy at transistor level has been added. In this technique each transistor of the various building blocks (Ex-OR gate, Multiplexer) of the voter circuit is replaced by a quadded-transistor structure. Quadded transistor structure provides built in immunity to all single defects as well as a large number of multiple defects. To evaluate the effectiveness of the voter circuit an IC layout in 90nm CMOS technology is developed. FPNI layout using qNAND hypercell is also designed and analysed. By simulation procedure it has been shown that the proposed fault tolerant voter circuit works properly as a majority voter in different faulty conditions of a TMR system. Moreover, it has been shown that in the presence of internal hardware failure (failure in transistor level) the voter circuit works properly.

A NEW CASCADABLE ADIABATIC LOGIC TECHNIQUE

There are several techniques to realize adiabatic logic but most of them require compliment forms. In this work, a new adiabatic logic technique has been proposed which is capable of working with a single time varying supply voltage. The most attractive feature of the proposed technique is that there is no need of complementary inputs. The proposed adiabatic logic has been implemented by adding charging and discharging paths in the existing standard CMOS logic, using diodes and capacitors. Further, various logic circuits such as INVERTER, NAND, NOR, half adder and positive edge triggered D-flip-flop have been implemented using the proposed adiabatic logic technique. A mathematical expression has been developed to explain the energy dissipation in proposed adiabatic logic technique. All the proposed circuits have been simulated for a time varying supply voltage, peak value of 0.9 Volt. A comparison of these logic circuits designed using 90nm TSMC MOS model, with their standard CMOS based structure shows a large improvement in power consumption to the tune of 60%. The results show that a considerable reduction in power dissipation can be achieved with the proposed adiabatic logic technique and thus we can save significant amount of energy compared to conventional CMOS circuits.

Ultra-Low-Voltage Self-Body Biasing Scheme and Its Application to Basic Arithmetic Circuits

The gate level body biasing (GLBB) is assessed in the context of ultra-low-voltage logic designs. To this purpose, a GLBB mirror full adder is implemented by using a commercial 45 nm bulk CMOS triple-well technology and compared to equivalent conventional zero body-biased CMOS and dynamic threshold voltage MOSFET (DTMOS) circuits under different running conditions. Postlayout simulations demonstrate that, at the parity of leakage power consumption, the GLBB technique exhibits a significant concurrent reduction of the energy per operation and the delay in comparison to the conventional CMOS and DTMOS approaches. The silicon area required by the GLBB full adder is halved with respect to the equivalent DTMOS implementation, but it is higher in comparison to conventional CMOS design. Performed analysis also proves that the GLBB solution exhibits a high level of robustness against temperature fluctuations and process variations.

Recent Development in Efficient Adiabatic Logic Circuits and Power Analysis with CMOS Logic

Abstract Power consumption plays a major role in present day VLSI design technology. The demand for low power consuming devices is increasing rapidly and the adiabatic logic style is said to be an attractive solution. This paper investigates different methods for designing adiabatic logics such as CMOS adiabatic circuits, ECRL, PFAL, CAL, DFAL, 2N-2P and 2N-2N2P. A lot of research has been already done using adiabatic technique. This paper presents a review of above mentioned adiabatic inverters in literature from basic elements. The SPICE simulation results show the comparison of power dissipation between conventional CMOS circuits and adiabatic logic based circuits.