Conventional Circuit Simulators Research Articles

A compact Non-Quasi-Static small-signal model for GaN HEMT

In this work, we introduce a compact Non-Quasi-Static (NQS) model for the long-channel Gallium nitride high-mobility field effect transistor based on charge-based EPFL (École Polytechnique fédérale de Lausanne) HEMT model implemented in Verilog-AMS modeling language. The proposed model has been validated for the low-frequency (quasi-static) operating region as well as high frequencies up to sub-terahertz. This model has been derived from the analytical solution of the drift–diffusion and continuity equations based on physically valid assumptions. Polynomial approximation was used to make the model design-oriented and compatible with conventional circuit simulators for designing microwave circuits. Intrinsic trans-admittance parameters, obtained from the model for two devices with channel lengths of 1μm and 10μm has been validated with TCAD simulation results. Besides, the scattering parameters for the GaN HEMT equivalent circuit, have been validated with TCAD simulations and with our previous work, which already validated with experimental data. These results confirm the effectiveness of the proposed compact model for circuit simulations.

Low-Cost Error Estimation for Fast and Stable Circuit Simulation Using Modified Inversion of the Laplace Transform

The modified numerical inversion of the Laplace transform (NILT <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$n$ </tex-math></inline-formula> ) has been recently proposed as a fast and provably stable numerical simulation for general circuits. However, its efficiency has revealed challenges that are not typically seen in the conventional circuit simulators that rely on the classical SPICE engine. More particularly, the issue of estimating the approximation error is one problem that has not been adequately addressed using efficient approaches. The work presented in this article addresses this issue by deriving a formula that is used to estimate the approximation error for a given length of the time step. The proposed method is based on the relation between NILT <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$n$ </tex-math></inline-formula> and NILT0, which allows the error to be estimated via a series of forward/backward substitutions. The numerical simulations show the accuracy of the proposed method to predict the approximation error at an incremental computational cost.

On the modeling of amplitude-sensitive electron spin resonance (ESR) detection using voltage-controlled oscillator (VCO)-based ESR-on-a-chip detectors.

In this paper, we present an in-depth analysis of a voltage-controlled oscillator (VCO)-based sensing method for electron spin resonance (ESR) spectroscopy, which greatly simplifies the experimental setup compared to conventional detection schemes. In contrast to our previous oscillator-based ESR detectors, where the ESR signal was encoded in the oscillation frequency, in the amplitude-sensitive method, the ESR signal is sensed as a change of the oscillation amplitude of the VCO. Therefore, using VCO architecture with a built-in amplitude demodulation scheme, the experimental setup reduces to a single permanent magnet in combination with a few inexpensive electronic components. We present a theoretical analysis of the achievable limit of detection, which uses perturbation-theory-based VCO modeling for the signal and applies a stochastic averaging approach to obtain a closed-form expression for the noise floor. Additionally, the paper also introduces a numerical model suitable for simulating oscillator-based ESR experiments in a conventional circuit simulator environment. This model can be used to optimize sensor performance early on in the design phase. Finally, all presented models are verified against measured results from a prototype VCO operating at 14 inside a 0.5 magnetic field.

A Non-Linear Lumped Model for the Electro-Mechanical Coupling in Capacitive MEMS Microphones

This work provides an analytical non-linear model for the capacitive transduction in MEMS transducers with perforated counter-electrodes, especially applicable to capacitive MEMS microphones. Starting from an electrostatic description of a perforated unit cell of the transducer, analytical formulations of the variable capacitance and electrostatic forces are derived, accounting for the deflection profile of a clamped circular plate. A lumped implementation into conventional circuit simulations tools is enabled via behavioral modeling based on hardware description languages, such as Verilog-A. Therefore, the analytical model is approximated via Taylor series expansions, allowing for a stable and non-linear behavioral implementation. The resulting model finally enables both a small- and large-signal analysis of capacitive MEMS microphones, precisely accounting for non-linearities in the capacitive transduction. This allows to simulate the harmonic distortion of the microphone's output signal and to account for electrostatic spring-softening in simulations of its bias voltage dependent sensitivity.

Investigation of the Effects of 1/fNoise on Superconducting Circuits

We analyzed the influence of 1/f noise in superconducting circuits on circuit operation using an analog circuit simulation. We devised a circuit simulation considering the 1/f noise using a conventional analog circuit simulator that can analyze the influence of thermal noises. In the circuit simulation, we used a passive filter that has a transfer function of -3 dB/oct to convert the Gaussian distributed white noise into the 1/f noise. We analyzed the gray zone characteristics of both the quantum flux parametron (QFP) and a single-flux-quantum current comparator considering both thermal and 1/f noises; the calculated gray zone width characteristics agree well with experimental results. Moreover, the influence of the 1/f noise is dominant in low operating speed regions for the QFP. These results indicate that the influence of the 1/f noise should be carefully considered to design superconducting circuits driven by a low-frequency clock.

Erratum to “Large-Signal Model of Graphene Field-Effect Transistors—Part I: Compact Modeling of GFET Intrinsic Capacitances” [Jul 16 2936-2941

We present a circuit-compatible compact model of the intrinsic capacitances of GFETs. Together with a compact drain current model, a large-signal model is developed combining both models as a tool for simulating the electrical behavior of graphene-based integrated circuits, dealing with the dc, transient behavior, and frequency response of the circuit. The drain current model is based on a drift-diffusion mechanism for the carrier transport coupled with an appropriate field-effect approach. The intrinsic capacitance model consists of a 16-capacitance matrix including self-capacitances and transcapacitances of a four-terminal GFET. To guarantee charge conservation, a Ward–Dutton linear charge partition scheme has been used. The large-signal model has been implemented in Verilog-A, being compatible with conventional circuit simulators and serving as a starting point toward the complete GFET device model that could incorporate additional nonidealities.

Dynamic Phasor-Based Analysis of Unbalanced Three-Phase Systems in Presence of Harmonic Distortion

In this paper, a frequency-based analytical approach for dynamic analyzing of unbalanced three-phase systems in the presence of harmonic distortion using sequence domain is put forward. As will be shown, classical symmetrical components proposed by Fortescue is not applicable under nonsinusoidal periodic condition. In such cases, generalized symmetrical components proposed by Tenti et al. can be used to calculate sequences from phase domain values. However, it introduces a new sequence component called residual component, which has a different value for each phase and cannot be directly obtained based on sequence networks. To such aim, using dynamic harmonic domain, an approach that makes it possible to use features of classical symmetrical components and modify the outputs to compute sequences based on the concept of generalized symmetrical components is proposed. Moreover, it is shown that using equivalent circuit for triplen harmonics is essential to find a relation between residual components since if sequences are connected in parallel, it is not possible to modify results of classical symmetrical components and this equivalent circuit should be directly analyzed. Time domain software is used to perform conventional lumped circuit simulation and validate the time domain responses resulted from DHD.

An Evaluation of the Equivalent Inverter Modeling Approach

Accurate modeling of CMOS logic gates for timing and power characterization is a very important task in integrated circuits technology since it facilitates significantly the design phase. Parametric models provide flexibility in determining the circuit performance in various design corners. However, the direct analysis of a complex CMOS gate aiming in an analytical and parametric model is a difficult and cumbersome task. An alternative way to model these gates is by using the equivalent inverter approach. According to this, an inverter with appropriate transistor widths is defined in order to present the same response with the complex gate it models. The challenge with this approach is to propose a simple method to predict the appropriate transistor widths of the equivalent inverter. Then, an analytical model for the CMOS inverter can be used to provide estimates for the complex gates. In this paper, a macro-modeling method is proposed for determining the transistor widths of the equivalent inverter and a technique for providing parametric expressions for these widths in terms of input transition time, output capacitive load, initial transistor width, supply voltage and temperature. A tool is developed to provide timing and power characterizations for the cells of a digital cell library, much faster than conventional numerical circuit simulators. The results prove the efficiency of the equivalent inverter approach in modeling complex gates.

Design and Implementation of High Performance Miniature Uniplanar Microwave Low Pass Filter up to 15GHz

Objectives: This work is introduced to design, implementation and specific analysis of printed miniature uniplanar micro strip low pass filter having a cut off of 15GHz on RT/duroid 6010.2 substrate. Methods/Statistical analysis: Besides, the paper examines simulated responses of three circuits which are predominantly lumped element circuit, stepped impedance and EM simulation with respect to conventional design circuit simulations where in both the design strategy will match the tested results. Findings: This proposed work comprises low pass filter design, lumped design and basic design by using only micro strip lines technology. The EM Structure sight design technique gives good sharp cut-off frequency response when compare with other technique towards low insertion loss which brings about having extraordinary concurrence for incredible relationship. Predominantly, AWR microwave office tool is used for designing and analysis. Application/ Improvements: The proposed design configuration will have more extensive application in advancements like 5G, Satellite, radars, Port Vessel Traffic Services and military communication system.

Large-Signal Model of Graphene Field-Effect Transistors—Part I: Compact Modeling of GFET Intrinsic Capacitances

We present a circuit-compatible compact model of the intrinsic capacitances of graphene field-effect transistors (GFETs). Together with a compact drain current model, a large-signal model of GFETs is developed combining both models as a tool for simulating the electrical behavior of graphene-based integrated circuits, dealing with the DC, transient behavior, and frequency response of the circuit. The drain current model is based in a drift-diffusion mechanism for the carrier transport coupled with an appropriate field-effect approach. The intrinsic capacitance model consists of a 16-capacitance matrix including self-capacitances and transcapacitances of a four-terminal GFET. To guarantee charge conservation, a Ward-Dutton linear charge partition scheme has been used. The large-signal model has been implemented in Verilog-A, being compatible with conventional circuit simulators and serving as a starting point toward the complete GFET device model that could incorporate additional non-idealities.

磁歪式振動発電スイッチを用いた電池フリーリモコンの実用化に関する研究

This research aims at realization of a battery free remote controller by switch type magnetostrictive-power generator using an iron-gallium alloy (Galfenol). The principle of power generation is based on parallel beam structure of Galfenol plate and yoke, by which input mechanical energy by pushing button is converted to electrical energy via free vibration. Our proposing controller consists of the generator, power conversion circuit (rectifier and capacitor), DC-DC converter and wireless module. In order to maximize the energy at the capacitor, the conversion circuit should be designed by considering equivalent model of the generator, coupling of mechanical and electrical circuit. We identified the parameters of the model by measurements of displacement and vibration, which the parameters were used to design the conversion circuit by LTSPICE, conventional circuit simulator. The combinations of capacitors in rectifier circuit providing the maximum energy at simulation and experiment were coincident, which verifies the validity of our design method. The operating condition of converter and module was investigated and twice of switch operation of combined system could send wireless sensor signal.

Circuit level simulation of MRI receive chain using excitation derived from images

ABSTRACTWe introduce a novel component‐level simulation method with which to characterize the performance of the electronic interfaces and circuitry of a magnetic resonance imaging (MRI) receiver. The Matlab‐based toolbox first reconstructs idealized coil free induction decay signals from real MR images, then uses these signals to drive a transistor‐level and extracted‐layout simulation of the desired receiver architecture. The simulated receiver's outputs are read back into the toolbox, which then reconstructs the MR images. By comparing the reconstructed images with the original ones, important design characteristics, such as the circuit's noise figure, linearity, phase noise, and inter‐channel coupling, can be investigated in terms of image quality. To validate the method, a new MRI receiver architecture is designed and simulated. The architecture is a 16‐channel multiplexer, designed for a commercially available 0.35 μm CMOS technology, and employs both frequency‐division and time‐division multiplexing to form a combined output signal. The SNR degradation and the circuit's linearity determined from the MR images compare well with the SNR and linearity point predictions from conventional circuit simulations. © 2015 Wiley Periodicals, Inc. Concepts Magn Reson Part B (Magn Reson Engineering) 44B: 102–113, 2015

An Accurate and Verilog-A Compatible Compact Model for Graphene Field-Effect Transistors

The present paper provides an accurate drift-diffusion model of the graphene field-effect transistor (GFET). A precise yet mathematically simple current-voltage relation is derived by focusing on device physics at energy levels close to the Dirac point. With respect to previous work, our approach extends modeling accuracy to the low-voltage biasing regime and improves the prediction of current saturation. These advantages are highlighted by a comparison study of the drain current, transconductance, output conductance, and intrinsic gain. The model has been implemented in Verilog-A and is compatible with conventional circuit simulators. It is provided as a tool for the exploration of GFET-based integrated circuit design. The model shows good agreement with measurement data from GFET prototypes.

DESIGN AND SIMULATION OF PRINTED MICRO STRIP LOW PASS FILTER BASED ON THE ELECTROMAGNETIC MODELS 18GHZ PRINTED MICROSTRIP LOWPASS FILTER USING X-MODELS

This paper presents the Design, Simulation and characterization of Printed Micro strip Low Pass Filter based on 15 mil Alumina substrate. Simulations show a comparison between a pure EM simulation with EM Sight and a more efficient hybrid approach that combines EM analysis (using X-Models) with conventional circuit simulations and both approaches match the measured data. Furthermore, the proposed paper has four different low pass filter designs, lumped design; basic designs uses only micro strip lines; advanced design uses multiple edge coupled micro strip lines, EM sight design provides a very sharp cut-off frequency response with low insertion loss, results having great agreement with excellent correlation. Tuning and Optimization of the design is carried out using AWR Microwave office tool.

Radio-Frequency Performance of Carbon Nanotube-Based Devices and Circuits Considering Noise and Process Variation

This paper provides a global overview of the radio-frequency (RF) performance potential of carbon-nanotube field-effect transistors (CNFET), which for the first time includes the impact of noise. We develop noise and manufacturing process variability extensions for the Stanford CNFET compact model, implemented in Verilog-A and compatible with conventional circuit simulators. CNFET figures-of-merit (FoM) are determined both on the device and on the circuit level. Compared to silicon technology, CNFET devices show much better performance in terms of most of the RF-CMOS requirements of the International Technology Roadmap for Semiconductors. FoM projections for basic RF building blocks (low-noise amplifier and oscillator) show that good performance can already be obtained with simple circuit topologies. The main advantage of CNFET circuits yet lies in easily reaching operation frequencies of several hundreds of gigahertz, which are hard to be exploited by silicon technologies at similar technology nodes.

A Rigorous Circuit Model for Simulation of Large-Scale Photonic Integrated Circuits

A rigorous circuit model for the simulation of large-scale photonic integrated circuit (PIC) is proposed and validated. Different from the conventional circuit theory, both guided and radiation fields are taken into consideration in the circuit model. A PIC of arbitrary size and complexity is partitioned into a collection of basic circuit elements interconnected via physical and virtual ports. The model parameters describing the terminal properties of the circuit elements are extracted by numerical techniques for photonic device simulation such as FDTD method. The performance of the entire PIC can be simulated by conventional circuit simulation algorithms based on the complex scattering matrix formalism. In contrast with the existing numerical simulation techniques, the circuit model and the simulation methodology are more flexible, efficient, and scalable for the analysis of large-scale PICs.

Equivalent circuits for implicit Runge-Kutta methods in circuit simulators for nonlinear circuits

This paper describes a method of implementing RadauIIA and LobattoIIIA of implicit Runge-Kutta formulas into circuit simulators for nonlinear circuits as numerical integration. These implicit Runge-Kutta methods have high orders and are A-stable. Equivalent circuits at discrete time for linear and nonlinear elements are proposed. Circuits at times between past and present time are needed in addition to the equivalent circuit at present time. Solutions at intermediate and present times must be estimated simultaneously. So, the size of equivalent circuit becomes larger than the numerical integration in conventional circuit simulators. However, since the orders of these algorithms are high, this problem is solved by using larger time step for numerical integration compared to conventional methods to save calculation time. The implicit Runge-Kutta and conventional methods are compared in terms of accuracy and computational costs using example circuits.

A Practical Iron Loss Calculation for AC Filter Inductors Used in PWM Inverters

A novel iron loss calculation method is proposed based on an iron loss map for an AC filter inductor used in a pulsewidth-modulation (PWM) inverter. The iron loss map, previously reported by the authors, is created by measuring the dynamic minor loop on the B-H plane, and this is used for the calculation of inductor iron loss in the dc chopper circuit. However, in the case of an AC filter inductor used in a PWM inverter, the iron loss map cannot be directory applied to the iron loss calculation. In this paper, an iron loss calculation for an ac filter inductor is presented by expanding the loss map method. We describe the principle of expansion and the practical procedure for the calculation, which utilizes the loss map and a conventional circuit simulator. Iron loss for the ac filter inductor under some typical modulation methods of the PWM inverter are calculated and discussed with regard to the relation between the modulation methods and iron loss. The calculated results are verified using experimental results from a 500-W inverter setup. The inductor loss and conversion efficiency of the PWM inverter are measured for each modulation method.

Simulation method for transmission-type radio-frequency single-electron transistor (RF-SET) operation by SPICE

An efficient simulation method for transmission-type radio-frequency single-electron transistors (RF-SETs) is developed. By introducing equivalent circuits of propagating microwaves through RF cables, we solve the master equation for RF-SETs self-consistently by using the conventional circuit simulator SPICE together with the SET current model. By examining transmitted waves from the transmission-type RF-SET, we show that the developed method successfully reproduces the numerical reference methods (calculated self- consistently). We also show that our method provides simple and fast ways to simulate and analyze RF-SETs even under complicated circuit geometry and in high frequencies over GHz. Based on the developed simulation method, we introduce the modulation technique to estimate the charge sensitivity of the transmission-type RF-SET.

A weak-to-strong inversion mismatch model for analog circuit design

This paper reports on a new CMOS transistor mismatch model that is continuous from weak to strong inversion. The model is completely described by analytical equations which are based on either the ACM or EKV transistor models. Large signal ACM and EKV transistor equations including the relevant parameters for mismatch are used for fitting the measured data. Five parameters are found to be relevant for predicting mismatch from weak to strong inversion: specific current I s , threshold voltage V T0, gamma ?, ? o (dependent on mobility degradation and source-drain series resistances), and ? e (dependent on velocity saturation and drain series resistance). Arrays of NMOS and PMOS transistors of 30 different sizes were fabricated in a 0.35 μm CMOS process. For each transistor size 12 different curves were measured. Different mismatch parameter extraction methods were used and compared. Average current mismatch prediction error was found to be in the range between 4 and 10% in the whole bias range from weak to strong inversion. Worst case mismatch prediction errors were in the range 23---61%. Since mismatch was predicted for a large number of sizes, the model could be implemented in a conventional circuit simulator to predict transistor mismatch not only as a function of transistor area but as function of transistor width and length independently. It was found that minimum mismatch is not always achieved by square transistors, and that mismatch is less sensitive to reducing width than to reducing length.