Conventional Circuit Simulators Research Articles

Modelling delay and crosstalk in VLSI interconnectfor electrical simulation

A method for extracting the multi-pen equivalent network of a system of m distributed RC lines is presented. The technique enables the time delays and crosstalk between interconnects to be efficiently analysed by employing conventional circuit simulators.

Synthesis of time-domain models for interconnects having 3-D structure based on FDTD method

This work describes an efficient method to simulate transient responses of multilayer and multiconductor interconnects having three-dimensional structure. First, the impulse responses between any pair of terminals of lines are obtained by the finite-difference time-domain (FDTD) method, Next, the frequency responses are obtained by the Fourier transform of these transient waveforms. The time-domain models are synthesized from the frequency responses by using the least-square approximation and the complex frequency-hopping technique. Finally, with this model, the transient responses are rapidly simulated by the conventional circuit simulators. In conclusion, the validity of this method is verified by comparison with the time-consuming FDTD simulation.

Simulation of Si multiple tunnel junctions

Single electron multiple tunnel junctions (MTJs) provide a useful means of achieving Coulomb blockade effects using silicon technology. A blocking dot model is developed for the simulation of these MTJs. Our simulation uses a single-electron simulator integrated into a SPICE-type conventional circuit simulator, thus allowing for the simulation of MTJ-based memory cells.

Implementation of the local reference node concept for spatially distributed circuits

Large spatially distributed microwave and millimeter-wave systems involve the interaction of linear and nonlinear circuits with their electromagnetic environment. Here a circuit-level approach to the modeling of circuit-field interactions is developed. ©1999 John Wiley & Sons, Inc. Int J RF and Microwave CAE 9: 376–384, 1999

A simple rate-equation-based thermal VCSEL model

Motivated by the potentially large number of devices and simulations involved in optoelectronic system design, and the associated need for compact optoelectronic device models, we present a simple thermal model of vertical-cavity surface-emitting laser (VCSEL) light-current (LI) characteristics based on the laser rate equations and a thermal offset current. The model was implemented in conventional SPICE-like circuit simulators, including HSPICE, and used to simulate key features of VCSEL LI curves, namely, thermally dependent threshold current and output-power roll-over for a range of ambient temperatures. The use of the rate equations also allows simulation in other non-dc operating regimes. Our results compare favorably to experimental data from three devices reported in the literature.

Hybrid Circuit Simulator Including a Model for Single Electron Tunneling Devices

A hybrid circuit simulator has been developed that incorporates elements of single electron devices into the conventional circuit simulator SPICE (Simulation Program with Integrated Circuit Emphasis). The elements can consist of an arbitrary network of tunnel junctions and capacitors, whose characteristics are calculated using a master equation method. By employing the hybrid circuit simulator, we studied a turnstile device feeding the input of a complementary metal-oxide-semiconductor (CMOS) inverter, and were able to more successfully demonstrate the transfer of electrons through the turnstile one by one in SPICE.

Full-wave analysis of high-speed interconnects using complex frequency hopping

Accurate simulation of large interconnect networks has become a necessity to address signal-integrity issues in current high-speed very-large-scale-integration designs. To accurately characterize a dispersive system of interconnects at higher frequencies, a full-wave analysis is required. However, conventional circuit simulation of interconnects with full-wave models is extremely CPU expensive. Recently published moment-matching techniques provide a generalized approach to lumped/distributed circuit response approximations. However, these techniques are based on quasi-transverse electromagnetic mode (TEM) assumption and have no mechanism to handle full-wave models. In this paper, we present a new method to extend model-reduction techniques for simulation of full-wave models. The following three new results are presented in this paper: 1) a generalized method to combine modal results from a full-wave analysis into circuit simulators; 2) a new algorithm for moment generation involving full-wave models; 3) deviations associated with quasi-TEM approximations compared to full-wave models at higher frequencies. The proposed algorithm yields a speed up of 1 to 2 orders of magnitude for a comparable accuracy with conventional techniques. In addition, the proposed method can be used for a mixed simulation involving distributed models with frequency dependent/independent RLCG parameters, full-wave interconnect models and measured subnetworks along with nonlinear terminations.

FD-TLM electromagnetic field simulation of high-speed Josephson junction digital logic gates

The finite-difference transmission line matrix (FD-TLM) method is extended to modeling low-T/sub c/ Josephson junction (JJ) digital logic integrated circuits (IC's), providing comprehensive simultaneous time-domain, three-dimensional (3-D) full-wave electromagnetic field and JJ device analysis. Techniques for FD-TLM modeling of a Josephson Atto-Webber switch (JAWS), a two-junction superconducting quantum interference device (SQUID), and modified variable threshold logic (MVTL) logic gates are discussed and simulation results are presented. Interconnection lengths are intentionally short so that the full-wave FD-TLM simulation results can be validated with results of conventional quasistatic-based circuit simulations. Good agreement between the simulation techniques validates the FD-TLM JJ logic circuit modeling approach. In the FD-TLM method the electromagnetic behavior of the circuit is modeled from the material properties and dimensions of the circuit, avoiding separate extractions of parasitic capacitance and inductance as needed in conventional circuit simulations.

Layout to circuit extraction for three-dimensional thermal-electrical circuit simulation of device structures

In this paper, a method is proposed for extraction of coupled networks from layout information for simulation of electrothermal device behavior. The networks represent a three-dimensional (3-D) device structure with circuit elements. The electrical and thermal characteristics of this circuit representation are calculated with a circuit simulator. Spatial potential distributions, current flows, and temperature distributions in the device structure are calculated on the spatial coordinates. This simulation method can be placed between device simulation and (conventional) circuit simulation. It has been implemented in a circuit simulator and is demonstrated for simulation of self-heating in a bipolar low frequency power transistor. The main advantage of this simulation method is that not only the 3-D thermal behavior of the whole chip is simulated, but that this is also directly coupled to the electrical device behavior by means of the power dissipation and temperature distribution in the device. This offers the possibility for the circuit designer to simulate 3-D, coupled, thermal-electrical problems with a circuit simulator. As an example, the influence of the emitter contacting on the internal temperature and current distribution of a BJT is investigated.

FD-TLM modeling of Josephson junction circuits

Josephson junction circuits are capable of operating at high frequencies where a full-wave field simulation is needed to completely analyze the circuits. The FD-TLM time-domain full-wave electromagnetic field calculation method is extended to modeling high-speed Josephson junction (JJ) circuits by the incorporation of a model for the JJ. The JJ model implementation is described and is validated by excellent agreement between FD-TLM and conventional circuit simulations of the transient response of a JJ circuit having short interconnections. >

Delay and crosstalk simulation of high-speed VLSI interconnects with nonlinear terminations

A method for analysis of VLSI interconnects that contain both lossy coupled transmission lines and nonlinear components is presented. An equivalent time-domain macromodel is derived for the linear subnetworks that contain lossy coupled transmission lines. The macromodel takes the form of a set of ordinary differential equations. The method takes full advantages of the asymptotic waveform evaluation (AWE) technique, which offers two to three orders of magnitude speed-up relative to other methods with comparable accuracy. In addition, it does not require explicit evaluation of the dominant poles of the network. The proposed technique can be easily implemented within the framework of an existing conventional circuit simulator such as SPICE.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Analytic transient solution of general MOS circuit primitives

The exact analytic transient solution is presented for a general MOS circuit primitive. In the circuit primitive, I-V characteristics of transistors are modeled by quadratic equations and node voltages by piecewise-linear waveforms. The proposed MOS circuit primitive, of which an inverter is a special case, is shown to be more suitable for switch level and fast timing simulations than the commonly used inverter. For circuit simulation of medium-size digital circuits containing a few hundred transistors, the application of this analytic solution has resulted in two to three orders of speed improvement over the conventional circuit simulator. The speed improvement factor is expected to grow with the circuit size. It is also shown that the exact transient solution of a macromodel which models the charge sharing can be obtained in the same way.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Analysis of high-speed VLSI interconnects using the asymptotic waveform evaluation technique

The asymptotic waveform evaluation (AWE) technique provides a generalized approach to lumped RLC circuit response approximations. Two results are described: (1) generalization of the AWE method to handle interconnect models which contain distributed elements; and (2) application of the generalized AWE technique to the case where the distributed elements can be modeled as lossy coupled transmission lines. The generalized AWE technique is useful for delay and crosstalk estimation and can be used to evaluate transient responses of high-speed interconnect circuits with negligible error compared with conventional circuit simulators, while being two to three orders of magnitude faster.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Piecewise approximate circuit simulation

Conventional circuit simulation methods are inflexible and slow, especially for large circuits. Piecewise approximate circuit simulation, an alternative that can be more efficient and allows variable accuracy in the simulation process, is discussed. Thus, the tradeoff between accuracy and CPU time is in the hands of the user. SPECS (simulation program for electronic circuits and systems) is the prototype implementation of a piecewise approximate, tree/link based, event driven, variable accuracy circuit simulation algorithm that uses table models for device evaluation. The models can be built at various levels of accuracy, and concomitant levels of precision are reflected in the simulation results. SPECS has been benchmarked on some large, industrial circuits and has proven to be an efficient and reliable simulator. However, it suffers a penalty in run time while simulating stiff circuits, or circuits with a wide range of time constants. The authors present enhanced algorithms used in SPECS to ensure efficient steady-state computation for stiff circuits. >

Circuit simulations combined with the electromagnetic field analysis

In order to provide a means of rigorous simulation for wideband nonlinear microwave integrated circuits, the concept of a lumped device model is introduced into a three-dimensional, time-domain electromagnetic field analysis method. This makes it possible to perform both a circuit simulation including nonlinear lumped devices and an electromagnetic field analysis for distributed microwave components at the same time. As an example, the generation of picosecond pulses from a nonlinear transmission line circuit is simulated. Based on the results, the features and the validity of the method are discussed in comparison with conventional circuit simulations. >

Functional simulation of color signal processor for VTR by digital dynamics simulation language

AbstractWith the development of semiconductor integration, the technology has arrived at the stage of the system‐on‐chip. With the widespread use of application specific IC (ASIC), the small‐quantity production of diversified types is required. Then it is important to reduce the design period for the mixed analog/digital circuit.VTR color signal processing LSI is a typical mixed analog/digital circuit. It has the scale of 500 analog elements and 800 digital elements, and it is too time‐comsuming to simulate the operation of the whole LSI by the conventional circuit simulator. Thus, a functional simulator is required for the large‐scale mixed analog/digital LSI.This paper proposes a functional simulation, employing techniques of continuous system simulation. The technique is applied to the design of a mixed analog/digital circuit, where the conventional method has been unsatisfactory, and the method is shown to be useful in the Functional design of the circuit. The method is based on the modeling of the mixed analog function/circuit, and can be applied to the VTR color signal processing LSI.The functional simulation can easily be performed with the complete knowledge of the analog function. Consequently, the method can contribute greatly to the quality improvement of the design and the reduction of the design period.

Flexible architecture approach to knowledge-based analogue IC design

A new design methodology for knowledge-based analogue IC design is presented. Due to the nonlinear nature of the analogue design process, iterations are always necessary to achieve accurate and reliable designs. A prototype expert system design assistant and a conventional circuit simulator are used for the iterative design process. The expert system employed is capable of optimising circuit topologies, as well as circuit element geometries, to better satisfy the performance specifications. Circuit reconstruction is achieved through circuit primitive replacements and design equation substitutions. Circuit primitive and critical nodes are processed before layout generation to minimise undesired parasitic effects. Layout parasitics can be included optionally in the design optimisation step. Experimental results are shown, to demonstrate the effectiveness of the flexible architecture approach through iteration and the expert analogue design system.

Electrical-logic simulation and its applications

Electrical-logic (ELogic) is a form of circuit modeling and simulation that solves for the amount of time required for a network variable to make a particular change, rather than solving for the network variables at the given time point as in conventional circuit simulation. Three ELogic algorithms are presented. The algorithms are based on the nodal analysis method and provide a continuous speed-precision tradeoff between the circuit level and logic/switch level, as well as providing more accurate timing information than existing strength-oriented logic simulation or switch-level simulation at comparable speed. These ELogic algorithms have been used to implement both a simulator, ELOSIM, and a timing verifier, E-Crystal, and experimental results from these programs are also included.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Simplified analysis off arbitrary switched-capacitor networks

A general method is presented which allows a closed-form analysis of switchedcapacitor (SC) networks with several phases, arbitrary duty cycles and with nonideal operational amplifiers. The method is based on a new equivalent representation of SC networks in the zdomain and on flow-graph techniques. The equivalent z-domain representations of SC networks proposed in this paper are compatible with classical circuit-theory considerations, and they are simpler and require a smaller number of elements than the equivalent circuits previously proposed. The usefulness and efficiency of the method proposed is illustrated with some examples. Moreover, it is shown how to transform the z-domain SC networks into equivalent time-continuous (analogue) circuits to analyse them in the frequency and/or time domain by use of conventional general-purpose circuit simulation programs. A user-ready implementation on SPICE is also proposed.

Modeling MOS VLSI circuits for transient analysis

Modeling plays a significant role in the efficient simulation of VLSI circuits. By simplifying the models used to analyze these circuits, it is possible to perform transient analyses with reasonable accuracy at speeds of one or two orders of magnitude faster than in conventional circuit simulation programs. The author discusses the models that are used in the second-generation MOTIS timing simulator. The methods used have been applied to a wide variety of MOS digital integrated circuits. All MOS transistors are modeled as voltage-controlled current sources using multidimensional tables. The actual currents are computed by approximation using variation-diminishing tensor splines. Nonlinear device capacitances in the circuit are approximated using linear models which are derived from experimental simulations using a circuit simulator. At the subcircuit level, special structures in the circuit are identified automatically by a preprocessor and are modeled using macro-models. Driver-load MOS transistor gates and bootstrapped circuits are examples of these structures. Their modeling is achieved by an experimental process before implementation in the preprocessor. The simplifications in the device and circuit models presented here have provided a significant improvement in the speed of transient analysis for large MOS digital circuits with relatively little loss in accuracy. This has resulted in a viable design verification environment using MOTIS.