A weak-to-strong inversion mismatch model for analog circuit design

Abstract

This paper reports on a new CMOS transistor mismatch model that is continuous from weak to strong inversion. The model is completely described by analytical equations which are based on either the ACM or EKV transistor models. Large signal ACM and EKV transistor equations including the relevant parameters for mismatch are used for fitting the measured data. Five parameters are found to be relevant for predicting mismatch from weak to strong inversion: specific current I s , threshold voltage V T0, gamma ?, ? o (dependent on mobility degradation and source-drain series resistances), and ? e (dependent on velocity saturation and drain series resistance). Arrays of NMOS and PMOS transistors of 30 different sizes were fabricated in a 0.35 μm CMOS process. For each transistor size 12 different curves were measured. Different mismatch parameter extraction methods were used and compared. Average current mismatch prediction error was found to be in the range between 4 and 10% in the whole bias range from weak to strong inversion. Worst case mismatch prediction errors were in the range 23---61%. Since mismatch was predicted for a large number of sizes, the model could be implemented in a conventional circuit simulator to predict transistor mismatch not only as a function of transistor area but as function of transistor width and length independently. It was found that minimum mismatch is not always achieved by square transistors, and that mismatch is less sensitive to reducing width than to reducing length.