Conventional 6T SRAM Cell Research Articles

Leakage power attack resilient Schmitt trigger based 12T symmetric SRAM cell

In this paper, a new 12T Schmitt trigger based SRAM cell is proposed in 40 nm technology. The proposed SRAM cell is resilient to leakage power attack (LPA), which is one of the main concern in side-channel attack (SCA). The proposed SRAM cell is designed by incorporating two more transistors to the Schmitt Trigger based 10T SRAM cell and is having equal leakage current when the storage node (Q) is storing 0 and 1, thereby achieving the overall distribution overlap percentage of 97.5% as compared to 0.09% of overlap in case of Schmitt Trigger based 10T SRAM. The Hold Static Noise Margin (HSNM), Read Static Noise Margin (RSNM) and Write Margin (WM) of the proposed design are also increased by 38.14%, 58.11% and 20.29% respectively as compared to 6T. Moreover, the WTP of the LPAR 12T is 1.07× greater as compared to the conventional 6T SRAM cell.

A Single-Ended 9T SRAM Cell With Improved Noise Margin for Low-Power Applications Used in LEDoS

As a silicon-based microdisplay for Augment reality (AR), the high power dissipation of digital CMOS driver is a significant barrier to approaching the higher performance of microdisplay. In this paper, a new low-power SRAM cell with a single bitline is proposed to reduce the power dissipation of digital CMOS drivers. Compared with conventional differential 6T SRAM cell, the proposed 9T uses the single-ended read/write and read/write separation technology by reducing bitline and adding word lines, and write/read static noise margin (WSNM/RSNM) has been improved while the power dissipation is reduced effectively by stacking effect. When VDD is 0.8 V, the proposed cell achieves 1.4× and 2.2× improvement in WSNM and RSNM compared to D6T. Besides, the proposed cell consumes 1.4× less power during hold mode compared to D6T at VDD=0.8 V.

A Spintronic 2M/7T Computation-in-Memory Cell

Computing data-intensive applications on the von Neumann architecture lead to significant performance and energy overheads. The concept of computation in memory (CiM) addresses the bottleneck of von Neumann machines by reducing the data movement in the computing system. Emerging resistive non-volatile memory technologies, as well as volatile memories (SRAM and DRAM), can be used to realize architectures based on the CiM paradigm. In this paper, we propose a hybrid cell design to provide the opportunity for CiM by combining the magnetic tunnel junction (MTJ) and the conventional 6T-SRAM cell. The cell performs CiM operations based on stateful in-array computation, which has better scalability for multiple operands compared with stateless computation in the periphery. Various logic operations such as XOR, OR, and IMP can be performed with the proposed design. In addition, the proposed cell can also operate as a conventional memory cell to read and write volatile as well as non-volatile data. The obtained simulation results show that the proposed CiM-A design can increase the performance of regular memory architectures by reducing the delay by 8 times and the energy by 13 times for database query applications consisting of consecutive bitwise operations with minimum overhead.

Single-Ended 8T SRAM cell with high SNM and low power/energy consumption

ABSTRACT This paper introduces an 8T single-ended SRAM cell to improve stability and decrease energy consumption. It cuts the pull-down path to the storage node written ‘1’, enhancing the write ability. It uses an isolated read path to enhance the read stability with low power and energy consumption. At a supply voltage of 0.5 V, the read static noise margin, write margin, read energy, and write energy of the proposed cell are superior by 320%, 233%, 12%, and 26%, respectively, compared to the conventional 6T. We performed 5,000 Monte Carlo simulations in the 32 nm technology to evaluate read yields. The results show that our cell has 6.9x more yields than the conventional 6T SRAM cell. Therefore, the proposed cell can be a good option for high stability and low power/energy applications.

A Symmetric Novel 8T3R Non-Volatile SRAM Cell for Embedded Applications

This paper proposes a symmetric eight transistor-three-memristor (8T3R) non-volatile static random-access memory (NVSRAM) cell. Non-volatile operation is achieved through the use of a memristor element, which stores data in the form of its resistive state and is referred to as RRAM. This cell is able to store the information after power-off mode and provides fast power-on/power-off speeds. The proposed symmetric 8T3R NVSRAM cell performs better instant-on operation compared to existing NVSRAMs at different technology nodes. The simulation results show that resistance of RAM-based 8T3R SRAM cell consumes less power in standby mode and has excellent switching performance during power on/off speed. It also has better read and write stability and significantly improves noise tolerance than the conventional asymmetrical 6T SRAM and other NVSRAM cells. The power dissipation is evaluated at different technology nodes. Hence, our proposed symmetric 8T3R NVSRAM cell is suitable to use at low power and embedded applications.

A Reliable Low Standby Power 10T SRAM Cell With Expanded Static Noise Margins

This paper explores a low standby power 10T (LP10T) SRAM cell with high read stability and write-ability (RSNM/WSNM/WM). The proposed LP10T SRAM cell uses a strong cross-coupled structure consisting standard inverter with a stacked transistor and Schmitt-trigger inverter with a double-length pull-up transistor. This along with the read path separated from true internal storage nodes eliminates the read-disturbance. Furthermore, it performs its write operation in pseudo differential form through write bitline and control signal with a write-assist technique. To estimate the proposed LP10T SRAM cell’s performance, it is compared with some state-of-the-art SRAM cells using HSPICE in 16-nm CMOS predictive technology model at 0.7 V supply voltage under harsh manufacturing process, voltage, and temperature variations. The proposed SRAM cell offers 4.65X/1.57X/1.46X improvement in RSNM/WSNM/WM and 4.40X/1.69X narrower spread in RSNM/WM compared to the conventional 6T SRAM cell. Furthermore, it shows 1.26X/1.08X/1.01X higher RSNM/WSNM/WM and 1.71X/1.25X tighter/wider spread in RSNM/WM compared to the best studied SRAM cells. The proposed SRAM cell indicates 74.48%/1.41% higher/lower read/write delay compared to the 6T SRAM cell. Moreover, it exhibits the third-(second-) best read (write) dynamic power, consuming 29.69% (26.87%) lower than the 6T SRAM cell. The leakage power is minimized by the proposed design, which is 37.35% and 12.08% lower than that of the 6T and best studied cells, respectively. Nonetheless, the proposed LP10T SRAM cell occupies 1.313X higher area compared to the 6T SRAM cell.

A low‐leakage single‐bitline 9T SRAM cell with read‐disturbance removal and high writability for low‐power biomedical applications

AbstractThe design of power‐efficient SRAM cells is necessary for biomedical applications such as body area networks (BANs) to extent their battery life. SRAM cell's power consists of two main components, including leakage power and dynamic power, in which the former overcomes the latter in advanced technology. This paper presents a low‐leakage single‐bitline 9T (L2SB9T) SRAM cell. The proposed design is free from read‐disturbance issue and eliminates writing “1” problem. The results are carried out by utilizing HSPICE and 16‐nm CMOS PTM at a 0.7 V, 25°C, and under severe PVT variations. The proposed L2SB9T SRAM cell is comprehensively compared with other recently published SRAM cells including conventional 6T, write/read enhanced 8T (WRE8T), transmission‐gate 9T (TG9T), read‐disturb‐free 9T (RDF9T), fully differential 10T (Chang10T), data‐independent read port 10T (DIRP10T), and single‐bitline 11T (SB11T). It shows at least 1.26X/1.07X/1.01X improvement in read static noise margin (RSNM)/write static noise margin (WSNM)/write margin (WM). Furthermore, the leakage power is reduced by the proposed cell, at least 1.137X. Moreover, the suggested cell consumes the third/second best dynamic read/write power, which is 1.42X/1.37X lower than that of conventional 6T SRAM cell. The proposed L2SB9T SRAM cell performs its read/write operation reliably by showing at least 1.71X narrower speared in RSNM compared to the best SRAM cell and third best WM variability. For all these improvements, the proposed L2SB9T SRAM cell incurs a 4.20X/1.06X/1.808X penalty in read delay/write delay/layout area when compared with the best SRAM cells, that is, the Chang10T/6T/6T.

Thermal Stability Analysis of Single-Ended 9T-ST Robust SRAM Cell for Near-Threshold Operation

This paper presents a single-ended Schmitt Trigger-based 9T SRAM cell, significantly improving thermal stability for real-time memory applications on a chip operated in a high radiation environment. The proposed single-ended 9T-ST SRAM cell has 73% and 13% improvement in read stability, 42% and 13% improvement in hold stability from 6T and 10T SRAM cells, respectively. The read stability of the proposed SRAM cell is compared with the conventional 6T SRAM cell, which is designed and tested for 23000 MC simulation samples to protect it from read failure. During read operation, the impact of temperature variation on the performance of memory cells is observed using Monte Carlo simulation for a temperature change from 20∘C to 60∘C, as 5%, 32%, and 48% variation in RSNM for 9T-ST, 10T-ST, and 6T SRAM cells, respectively. The proposed SRAM cell is designed and verified in the Synopsys Custom compiler.

Design of High-Reliability Memory Cell to Mitigate Single Event Multiple Node Upsets

As technology scaling down, the sensitivity of SRAM cells to radiation-induced Single Event Upsets (SEUs) increases, and Single Event Multiple Node Upsets (SEMNUs) due to charge sharing has also become one of the major concerns in memory cell designs. In this paper, a high-reliability radiation hardened memory cell (RH-14T) is proposed to mitigate SEMNUs. SPICE simulations and 3D technology computer aided design mixed-mode simulations were performed to verify the high robustness of the RH-14T cell to SEUs. Compared with previous radiation hardened memory cells, the proposed RH-14T cell has similar read access time, smaller write access time, and the read access time and write access time are less sensitive to process variations. The Read Static Noise Margin (RSNM) and Write Margin (WM) of the RH-14T cell are larger than those of the unhardened conventional 6T SRAM cell. The improvement of reliability is often a trade-off with area, power consumption and performance. In order to achieve high reliability, the RH-14T cell employs more transistors, so it has 1.5 times the power consumption overhead of 6T and a larger area penalty.

A highly reliable radiation hardened 8T SRAM cell design

In this paper, a new Radiation Hardened By Design (RHBD) 8T SRAM cell is proposed that can tolerate single-event upset (SEU) in a radiation environment. According to the simulation results for 130 nm silicon-on-insulator (SOI) technology, the critical charge of the proposed 8T cell increases by 82.9% compared to the conventional 6T SRAM cell and by 62.5% compared to the other RHBD SRAM cell, the Soft-error-Tolerant-10T (ST-10T) cell. Pulsed laser testing was used for SEU sensitivity evaluation. Further, the energy threshold of the proposed cell increases by 122.3% and 90.8%, respectively, compared to the conventional 6T cell and the ST-10T cell. Moreover, the proposed cell has a lower leakage current, higher read current, and larger read static noise margin (RSNM) compared to the other two cells. The total ionizing dose (TID) effects on the proposed 8T SRAM cell were also studied, and the results show that the proposed cell is insensitive to TID.

Comprehensive Analysis of 7T SRAM Cell Architectures with 18nm FinFET for Low Power Bio-Medical Applications

The SRAM cells are used in many biomedical applications such as Pace makers,ECG devices,body area networks etc.,where power consumption will be the main constraint. The conventional 6T SRAM cell has reduced stability and more power consumption when technology is scaled resulting in supply voltage scaling, so other alternative SRAM cells from 7T to 12T have been proposed which can address these problems. Here a low power 7T SRAM cell is suggested which has low power consumption and condensed leakage currents and power dissipation. The projected design has a leakage power of 5.31nW and leakage current of 7.58nA which is 84.9 % less than the 7T SRAM cell without using the proposed leakage reduction technique and it is 22.4 % better than 6T SRAM and 22.1 % better than 8T SRAM cell when both use the same leakage reduction technique. The cell area of the 7T SRAM cell is 1.25µm2, 6T SRAM is 1.079µm2 and that of 8T SRAM is 1.28µm2all the results are simulated in cadence virtuoso using 18nm technology.

Restoration circuits for low power reduce swing of 6T and 8T SRAM cell with improved read and write margins

<span>This article clarifies about the variables that influence the static noise margin (SNM) of a static random-access memory. Track down the improved stability of proposed 8T SRAM cell which is superior to conventional 6T SRAM cell utilizing Swing Restored circuit with voltages Q and QB bar are peruse and Compose activity. This SRAM cell strategy on the circuit or engineering level is needed to improve read static noise margin (RSNM), write static noise margin (WSNM) and hold static noise margin (HSNM). This article relative investigation of conventional 6T, standard 8T and proposed 8T SRAM cells with improved stability and static noise margin is finished for 180 nm CMOS innovation. This paper is coordinated as follows: Introduction in area 1, The 6T SRAM cell are portrayed in segment 2. In area 3, proposed 8T SRAM cell is portrayed. In area 4, standard 8T SRAM cell. Segment 5 incorporates the simulation and results which give examination of different boundaries of 6T and 8T SRAM cells and segment 6 conclusions.</span>

A Low-Leakage Variation-Aware 10T SRAM Cell for IoT Applications

This paper presents a novel low-leakage 10T SRAM cell along with its new read circuitry. It utilizes isolated read path for the read operation that enhances the read stability of the cell as compared to conventional 6T SRAM cell. The proposed cell has been introduced for IoT applications where low power devices are the primary requirement in order to enhance the battery life. To minimize the leakage current, the PMOS transistor has been employed at the read circuitry which assists to minimize the leakage current due to induced stacking effect. The leakage current is 37.66%, 40.11% and 67.39% less as compared to 6T SRAM, 8T SRAM and RDPFC 9T SRAM cells, respectively. The read delay for the proposed cell is 39.80%, 89.13% and 42.33% less as compared to 6T SRAM, 8T SRAM and RDPFC 9T SRAM cells, respectively. Also, the results depict the speed improvement of 48.60%, 52.49% and 55.71% during write “0” and 46.97%, 57.5% and 54.52% improvement during write “1” operation as compared to 6T SRAM, 8T SRAM and RDFC 9T SRAM cells, respectively. The RSNM of the proposed cell is 649 mV that shows enhanced read stability over conventional 6T SRAM cell. The proposed cell proves its robustness against worst-case process variations. All the simulation work has been completed on the Cadence Virtuoso environment at 180 nm technology node.

A Novel Loadless 6T-SRAM Cell with Isolated Read Port

Conventional 6T SRAM cell parameters have degraded with scaling to newer technologies and reduced power supply voltages. This has led to numerous tradeoffs with respect to cell stability, performance, power, and area. In this paper, a novel Dual Port SRAM design has been introduced that aims at improving the read and write ability of the standard 6T SRAM cell. The simulations for the proposed structure have been performed on HSpice using PTM 32nm Technology node. The comparison of results with the standard cell showed an increase of 84.76% in read margins and 40.81% in the write stability. Also, the proposed design was found to be capable of writing at high frequencies as the minimum pulse width of WWL for a successful write operation was determined to be 25ps. Further, the design also improves in the areas of WTV, SVNM, WTP, SPNM

Darlington Based 8T CNTFET SRAM Cells with Low Power and Enhanced Write Stability

In this paper, a novel low power and high write margin Darlington based NCNTFET Darlington 8T SRAM cell is proposed. The power consumption of the proposed Darlington SRAM cell is compared with that of conventional 6T CNTFET and conventional 8T CNTFET SRAM cells. The power consumption of the proposed Darlington SRAM cells is very less as compared to that of conventional 6T and 8T CNTFET SRAM cells for all write, hold, and read operations. The write static noise margin (WSNM) of the proposed NCNTFET Darlington 8T cell is found to increase by 70.83% than that of both conventional 6T and 8T CNTFET SRAM cell. Effect of CNTFET parameters such as chiral vectors (m,n), gate oxide thickness (Hox), dielectric constant of gate oxide material (Kox), temperature, pitch value, number of carbon nano tubes (CNTs) and supply voltage (VDD), on the power performance, drain current (ID) and drain to source voltage (VDS) of the novel proposed Darlington SRAM cell are investigated. The write, hold, and read power consumption of proposed NCNTFET Darlington 8T SRAM cell is compared with that of some of the existing SRAM cells. The simulation is carried out using Stanford University 32 nm CNTFET model.

A read-disturb-free and write-ability enhanced 9T SRAM with data-aware write operation

ABSTRACT This paper presents a single-ended 9T SRAM cell with data-aware write-word-line structure to improve write ability, and a positive feedback sense amplifier (SA) to solve sensing challenge at an ultra-low voltage. The proposed 9T cell is well suited for bit-interleaving architecture in SRAM array. Simulation results indicate that at a 0.5 V supply voltage, the proposed SRAM cell achieves the same read static noise margin (RSNM) as that of conventional 8T SRAM cell, because the read-decoupled read buffer achieves read-disturb-free operation. While at the same supply voltage, its write margin (WM) is 2.68× compared with the 8T SRAM cell. As a result, a lower minimum operation voltage is achieved. Additionally, its leakage power consumption is reduced by 86.1% compared with the 8T SRAM cell in the 40-nm standard CMOS technology, TT corner, 25°C.

Simulation and Analysis of P-P-N 10T SRAM cell for IoT based devices

Ultra low power integrated circuits got the major attention due to its lower power dissipation in the era of Internet of Things (IoT) based smarter devices. In this context, a P-P-N based 10T SRAM cell has been designed and simulated on cadence virtuoso tool with GPDK 45nm technology node at supply voltage ranges from 0.6V to 1V. The various parameters such as static noise margin, read/write power, read/write delay of the 10T SRAM cell are determined out and compared with other considered topologies. It is interesting to notice that 10T SRAM cell shows commendable improvement in read static noise margin (RSNM) i.e. 36% and 46% as compared to conventional 6T and differential 8T SRAM cells respectively. The 10T SRAM cell also has reduction in read power of 38.52% and 38% as compared to conventional 6T and differential 8T SRAM cells respectively. The read delay of P-P-N based 10T SRAM cell is improved by 40% with compared to conventional 6T SRAM cell.

A data‐independent 9T SRAM cell with enhanced ION/IOFF ratio and RBL voltage swing in near threshold and sub‐threshold region

SummaryThe conventional 8T SRAM cell with isolated read port is suggested as an alternative to overcome the read‐write conflicts associated with 6T SRAM cell. However, in near threshold and sub‐threshold regions, 8T cell performance is limited by reduced ION/IOFF ratio, deteriorated RBL voltage swing, data dependency, and higher read failures, although the existing SRAM cells address some of these issues but still suffer from degraded performance due to the trade‐off between leakage and read currents. In this paper, a 9T SRAM cell with novel read port is proposed that aims for low and data‐independent leakages, high ION/IOFF ratio, and large RBL voltage swing in near threshold and sub‐threshold regions. The performance of the proposed cell is compared with 7T, 8T, 9T, and 10T cells at 32 nm technology node by simulating a column of 128 cells to demonstrate its versatility over others. The proposed cell shows enhanced ION/IOFF ratio (71.2X), large RBL voltage swing and data‐independent leakages at VDD = 0.3 V in comparison to the conventional 8T SRAM cell. The results at different PVT corners are also captured to validate the impeccable performance of the proposed cell irrespective of operating conditions.

Single-Ended 10T SRAM Cell with High Yield and Low Standby Power

This paper introduces a 10T single-ended SRAM cell with high stability and low static power. The read static noise margin is augmented by using a Schmitt-trigger inverter and decoupling the storage node from the read bitline by adding one transistor. Since writing “1” is difficult in single-ended SRAM cells, using proper capacitive coupling and also extra pMOS transistor as an access transistor mitigates the problem. To evaluate read, write, and hold yields, we performed 10,000 Monto Carlo simulations in the 32-nm technology, and the results show our cell has 7.5×, 1.4×, and 1.1 × more yields than that of the conventional 6T SRAM cell. The proposed cell also has the least static power consumption. This amount is 1.5× less than the conventional 6T at the supply voltage of 0.5 V.

Design and Stability analysis of CNTFET based SRAM cell

Carbon Nanotube Field Effect Transistor (CNTFET) has proved to be very beneficial for VLSI circuit designs in the nano scale range due to its amazing properties than MOSFETs. As we reduce the gate length of the device to below 45nm, we see a lot of changes in its parameters such as stability of the cell reduces, power consumption and delay increases which are different from the traditional MOSFETs. This becomes a serious issue when we try to take traditional MOSFETs scale down from this technology node. The main aim of this paper is to design CNTFET 6T SRAM memory cell which consumes less power and is highly stable at 32nm technology node. The Stanford model files have proved to be very good for the CNTFET devices, which simulates on 32 nm technology nodes in HSPICE tool. The results shown in this paper clearly indicate that the stability enhances by approx. 27.55% of the CNTFET SRAM cell with 37.44% improvement in the power consumption. Explicit analysis of the results shows that CNTFET based 6T SRAM cell has improved power consumption, less delay and high stability with improved read & write noise margin than conventional 6T SRAM cell.