A Low-Leakage Variation-Aware 10T SRAM Cell for IoT Applications

Abstract

This paper presents a novel low-leakage 10T SRAM cell along with its new read circuitry. It utilizes isolated read path for the read operation that enhances the read stability of the cell as compared to conventional 6T SRAM cell. The proposed cell has been introduced for IoT applications where low power devices are the primary requirement in order to enhance the battery life. To minimize the leakage current, the PMOS transistor has been employed at the read circuitry which assists to minimize the leakage current due to induced stacking effect. The leakage current is 37.66%, 40.11% and 67.39% less as compared to 6T SRAM, 8T SRAM and RDPFC 9T SRAM cells, respectively. The read delay for the proposed cell is 39.80%, 89.13% and 42.33% less as compared to 6T SRAM, 8T SRAM and RDPFC 9T SRAM cells, respectively. Also, the results depict the speed improvement of 48.60%, 52.49% and 55.71% during write “0” and 46.97%, 57.5% and 54.52% improvement during write “1” operation as compared to 6T SRAM, 8T SRAM and RDFC 9T SRAM cells, respectively. The RSNM of the proposed cell is 649 mV that shows enhanced read stability over conventional 6T SRAM cell. The proposed cell proves its robustness against worst-case process variations. All the simulation work has been completed on the Cadence Virtuoso environment at 180 nm technology node.