Gain Control Range Research Articles

Design of Mutiple Signal Generators based on DDS

The hardware circuit of the signal generator mainly includes the main control module, DDS module, Voltage-Controlled Gain Amplifier (VCGA) module, keypad module, and LCD display module. The main control module is based on the STM32F103C8T6 as the core controller, and the signal processing section employs the low-power, programmable AD9834 DDS device. The VCGA module utilizes the AD8367 module, providing a controllable 32dB gain range to offer a 20mV/dB output. The waveform voltage amplitude can be adjusted by manipulating the potentiometer on the module and fed back to the oscilloscope. Experimental results demonstrate that the signal generator can produce square waves, triangular waves, sine waves, and sweep frequency waves with stable output waveforms and high resolution. Specifically, the sine wave and triangular wave can be generated within the frequency range of 1kHz to 200KHz, the square wave within the range of 75kHz to 200kHz, and the sweep frequency wave with a sweeping range from 1kHz to 100kHz.

10‐GHz band 2 × 2 phased‐array radio frequency receiver with 8‐bit linear phase control and 15‐dB gain control range using 65‐nm complementary metal–oxide–semiconductor technology

AbstractWe propose a 10‐GHz 2 × 2 phased‐array radio frequency (RF) receiver with an 8‐bit linear phase and 15‐dB gain control range using 65‐nm complementary metal–oxide–semiconductor technology. An 8 × 8 phased‐array receiver module is implemented using 16 2 × 2 RF phased‐array integrated circuits. The receiver chip has four single‐to‐differential low‐noise amplifier and gain‐controlled phase‐shifter (GCPS) channels, four channel combiners, and a 50‐Ω driver. Using a novel complementary bias technique in a phase‐shifting core circuit and an equivalent resistance‐controlled resistor–inductor–capacitor load, the GCPS based on vector–sum structure increases the phase resolution with weighting‐factor controllability, enabling the vector–sum phase‐shifting circuit to require a low current and small area due to its small 1.2‐V supply. The 2 × 2 phased‐array RF receiver chip has a power gain of 21 dB per channel and a 5.7‐dB maximum single‐channel noise‐figure gain. The chip shows 8‐bit phase states with a 2.39° root mean‐square (RMS) phase error and a 0.4‐dB RMS gain error with a 15‐dB gain control range for a 2.5° RMS phase error over the 10 to10.5‐GHz band.

A Fully Integrated Low-Power Multi-Mode RF Receiver for BDS-3/GPS.

A fully integrated low-power area-efficient receiver using a low-intermediate frequency topology for BDS-3 and GPS L1 bands is presented in this paper. Accurate localization can be achieved without requiring off-chip low-noise amplifiers. The receiver bandwidths for GPS and BDS-3 are 2 MHz and 4 MHz, respectively. Digitally assisted calibration schemes, such as RC calibration, automatic gain control, and DC offset correction are integrated to resist the effects of the process, voltage, and temperature (PVT) variations. The receiver-fabricated in a standard 55 nm CMOS technology-provides a maximum gain of 113.2 dB, a gain control range of 61 dB, and a minimum noise figure of 1.74 dB under a 1.2 V supply. The receiver, with and without the frequency synthesizer that provides the local oscillator frequency, consumes 8.7 mA and 4.8 mA, with areas of 0.73 mm2 and 0.345 mm2, respectively.

A Linear-in-Decibel Automatic Gain Control Amplifier With Dual Mode Continuous Gain Tuning

A reconfigurable fully integrated automatic gain control (AGC) amplifier is presented which is based on a dual mode continuous gain adjustment variable-gain amplifier (VGA). The VGA is realized based on the current-steering structure, achieving a linear-in-dB gain tuned by AGC’s feedback voltage. A current division active load is proposed, which provides additional gain control range and realizes gain robustness to process and supply variations without extra calibration. Simulated with Cadence IC, the maximum gain variations due to process and supply variations are 3.5 dB and 2.6 dB, respectively. By using dual mode gain tuning technique, the VGA achieves a total gain range of 68.2 dB. Both bandwidth and gain of the VGA are adjusted independently. The AGC is realized in UMC 55-nm CMOS technology with 0.026 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core area. With the current division ratio K of 0.5, the proposed VGA achieves a linear-in-dB gain of 42.2 dB ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 30.0 to 12.2 dB) with less than 0.79 dB error. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 3 dB bandwidth can be adjusted from 80 MHz to 140 MHz and is insensitive to gain variations. The power dissipation is from 2.9 mW to 4.5 mW. This design features bandwidth scalability and the gain independent of bandwidth to achieve various applications.

Low-Power Decibel-Linear Programmable-Gain Amplifier With Complementary Current-Switching Technique

In this study, a low-power decibel-linear (dB-linear) programmable-gain amplifier (PGA) is proposed. Based on the complementary current-switching technique, the proposed PGA achieves a wider bandwidth, a large gain control range, and a low dB-linear error while reducing the DC power consumption compared with the conventional PGA. To verify this, the proposed PGA was implemented using a 65-nm CMOS process. It provides a dB-linear gain control range of 59.7 dB with 1-dB steps while achieving a dB-linear gain error of less than 0.29 dB. Under a 1-V supply voltage, the proposed PGA delivers a peak gain of 34.9 dB and a 3-dB bandwidth of 270 MHz, consuming only 0.6 mW DC power.

A V‐band digitally controlled low noise variable gain amplifier with 3.5° phase variation in 28‐nm bulk CMOS

AbstractThis paper presents a V‐band digitally controlled low noise variable gain amplifier (LNVGA) in 28‐nm bulk CMOS process. The amplifier includes three stages and the first stage is used to realize wideband high gain and low noise figure (NF). The gain control is implemented in the second and third stages with current steering and split cascode topology, respectively. A source degeneration inductor and a series inductor are introduced to reduce the phase variation in the second stage. The phase response function is analyzed, and the phase reduction of 1.2° is achieved. Moreover, with the combination of these two different topologies, the phase variation can be further reduced. The measurement results show the LNVGA has a peak gain of 16 dB with a 3‐dB bandwidth of 45–59 GHz. The measured gain control range is 0–16 dB in 16 different gain states and the minimum phase variation is 3.5° with power consumption of 23 mW.

A 27–43 GHz CMOS Body-Biased Digital Current-Steering VGA With 4 Bit and Low Phase Shift

This letter presents a broadband digital-controlled variable gain amplifier (VGA) on 65-nm CMOS process. A body-biased digital current-steering topology is proposed to enlarge the gain control range (GCR) of the VGA under low supply voltage. For phased-array applications, a phase compensation network is added to minimize the phase shift during the gain tuning. The proposed VGA achieves a small-signal gain of 16.3/16.1 dB at 28/38 GHz with a 3-dB gain bandwidth from 25.5 to 46 GHz. The measured phase variation is 2.32°/4.8° with a GCR of 8.7/8.4 dB at 28/38 GHz. The phase variation of the VGA is less than 5° and the rms phase error is less than 1.46° over a wide frequency band of 27–43 GHz covering multiple 5G bands.

Parasitic-Aware Simulation-Based Optimization Design Tool for Current Steering VGAs

Designing millimeter-wave variable gain amplifiers (VGAs) is very challenging owing to the parasitic effects of the interconnects of both active and passive devices. An automated parasitic-aware optimization RF design tool is proposed in this paper to address this challenge. The proposed tool considers the parasitic effects prior to layout. It employs a knowledge-aware optimization technique. The augmentation between parasitic-aware and knowledge-aware techniques speeds up the design process and leads to a design as close to the final design after finalizing the layout. The proposed tool gives limitless and guaranteed converged solutions in a wide range of RF frequencies. A four-bits current steering VGA design is used as a validation of the tool. The tool is tested on three different frequencies using the 65 nm-technology node. The three tested frequencies (7, 10, and 13 GHz) show a root mean square gain error at approximately 0.1 dB and a phase variation at approximately 3.5° within a 16-dB gain control range. To our knowledge, it is the first reported automated design tool for a current steering VGA.

Power and Noise Reduction of High-Frequency Variable Gain Amplifier

This work illustrates the design of the cell-based variable-gain amplifier (VGA) with less power consumption and improved noise margin. The variable gain amplifier is incorporated into the current wireless front-end modules. The body-bias technique in the n channel MOSFET (n-MOS) devices greatly aided in the power reduction of the cells. The device characteristics were fine-tuned to get better gain and bandwidth and reduced the supply voltage. This technique ultimately reduced the number of cell stages required to meet the expectation. The reduction of the supply voltage and the technology upscaling helped to improve the noise margin. The presented unit cell achieved accurate dB-linear characteristics across a wide tuning range, based on a unique gain control method with a combination of sub-threshold n-MOS and saturation n-MOS transistors as active loads. A 7-cell reconfigurable VGA is simulated in 0.18-[Formula: see text]m Complementary MOSFET technology to verify the concept. The simulation results showed that the bandwidth of the VGA is greater than 2.5[Formula: see text]GHz, while less than 0.78[Formula: see text]mW is consumed from a 1.5-V supply. A noise figure of 23.7[Formula: see text]dB is measured. Also, the VGA achieves a gain control range of 19[Formula: see text]dB with a gain error less than [Formula: see text][Formula: see text]dB or 26.3%. These results make the designed amplifier adequate for high-frequency applications.

An 18–50-GHz Δ–Σ Modulated Quasi-Continuous Digital Vector-Modulation Phase Shifter With Variable Gain Control

This letter presents a high precision wideband active vector-modulating phase shifter with high dynamic range gain control ability. Compared with conventional switching-filter phase shifter and vector-modulation phase shifter, this Δ -Σ modulated vector phase shifter can provide quasi-continuous phase and gain control capability. According to the experimental results, the dynamic range of gain control is greater than 35.5 dB. The output reflection is lower than -10 dB through the 18-50-GHz band, and the input reflection is lower than -10 dB from 18 to 45 GHz. The phase shifter occupies 700 μm x 900 μm on 0.13-μm SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology, and the core size is only 400 μm x 500 μm. After digital calibration, the proposed phase shifter has achieved the highest phase and gain control precision compared with the state-of-the-art digital controlled phase shifters.

A miniaturized 35 GHz 65‐nm CMOS digital‐controlled differential variable gain amplifier

AbstractThis paper presents a 35 GHz differential variable gain amplifier (VGA) with 4‐bit digital‐controlled gain‐tuning using 65‐nm CMOS process. Using the proposed miniaturized differential matching inductors, a core size of the VGA is only 0.53 0.26 mm. The digital gain control mechanism is achieved using the digital version current steering topology. The measured gain control range of the VGA is from 17.4 to 9 dB at 35 GHz with 16 different linear‐in‐dB gain states. Thus, this work achieves the maximum peak gain per unit core size and maintains a much better gain control range per unit core size. The measured root mean square gain error is &lt;0.29 dB and phase error is &lt; from 34 to 36.5 GHz.

An E-band Variable Gain Amplifier with 24 dB-control range and 80 to 100 GHz 1 dB bandwidth in SiGe BiCMOS technology

Abstract Analysis, design, and characterization of an E-band Variable Gain Amplifier (VGA) in SiGe BiCMOS commercial technology is presented. VGA topologies are compared in terms of their capability to contribute to receiver linearity and dynamic range. The proposed VGA is based on a Gilbert multiplier cell exploiting current cancellation to enhance control range and linearity. A 1 dB bandwidth ranging from 80 to 100 GHz, a 24 dB gain control range and a −11.5 dBm input 1 dB compression point have been measured.

A 20-Gb/s wideband AGC amplifier with 26-dB dynamic range in 0.18-μm SiGe BiCMOS

This paper presents a 20-Gb/s automatic gain control (AGC) amplifier in a 0.18-μm SiGe BiCMOS for high-speed applications. The proposed AGC amplifier compactly consists of a folded Gilbert variable-gain amplifier (VGA), a post amplifier (PA), a 50-Ω output buffer, and AGC loop including an open-loop peak detector (PD), a RC low-pass filter (LPF), and an error amplifier (EA). The AGC amplifier achieves the broadband characteristic by utilizing inductive peaking and capacitive degeneration as well as fT-doubler techniques to overcome the large parasitic capacitances. The proposed AGC circuits together with a linear VGA exhibits a wide gain control range of 45 dB for the received signal strength indication (RSSI). The measured AGC amplifier achieves a maximum gain of 21 dB and a -3-dB bandwidth (BW) of 20.6 GHz, which can support up to 25.4-Gb/s data rate. For the pseudorandom bit sequence (PRBS) length 231–1 with a bit-error rate (BER) of 10−12 at 20 Gb/s, the measured input dynamic range is 26 dB (20–400mVpp) and the peak-to-peak data jitter is less than 8 ps. The AGC amplifier consumes a power of 160 mW from a 3.3-V supply voltage and occupies an area of 850 μm × 850 μm.

A 24–28-GHz Four-Element Phased-Array Transceiver Front End With 21.1%/16.6% Transmitter Peak/OP1dB PAE and Subdegree Phase Resolution Supporting 2.4 Gb/s in 256-QAM for 5-G Communications

This article presents a power efficient 24-28-GHz four-element phased-array transceiver (TRX) front end (FE) for 5-G base stations and user equipment communications. A power efficient hybrid quadrature vector interpolation-based phase-shifting architecture is proposed to increase the TX and RX power efficiency and phase resolution. A transformer-based embedded T/R switch is proposed which minimizes TX and RX losses to ensure high TX output power and power efficiency while maintaining a low noise figure (NF) and extremely compact chip area. The 24-28-GHz four-element TRX FE is implemented in a 65-nm CMOS process (1P9M) for large-scale phased-array applications. The TX and RX paths achieve 0.8° phase resolution with <; 0.47°/0.17-dB RMS phase/gain error as well as 24-dB gain control range with 0.75-dB gain step and <; 0.1°/0.4-dB RMS gain/phase error over 24-30 GHz. The full TX path (including splitter and T/R switch) also achieves a measured 16.6-/18.9-dBm OP1dB/ P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> with 21.1%/16.6% PAE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">peak</sub> /OP1dB for each FE element while maintaining a minimum 4.4-dB NF in the full RX path (including combiner, T/R switch, and OFF-mode PA) at 28 GHz. Under the 64-/256-QAM modulation measurements, the full TX path achieves a state-of-the-art average output power of 13.5-/10.2-dBm per element (8.4%/3.5% full TX path PAE) with -26.4/-30.8 dB EVM and 27.8-/30.1-dB ACLR at 28 GHz, making the proposed TRX FE can be effectively deployed in both base stations and user equipment for 5-G communications. The chip size of the four-element TRX FE excluding I/O pads is only 3.4×1.1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A DC to 220-GHz High-Isolation SPST Switch in 22-nm FDSOI CMOS

A wideband single-pole single-throw (SPST) switch covering the dc to 220-GHz frequency range is presented in this letter. A four-element distributed topology is used to extend operation to the upper millimeter-wave band. With a combination of front-gate and back-gate biasing, unique to fully depleted silicon-on-insulator (FDSOI) MOSFETs, and enabled by the thick metal/dielectric backend of the technology, the switch achieves an insertion loss of 3.1 dB and an isolation of 37 dB at 220 GHz, as well as a peak isolation of 58 dB at 200 GHz, without deembedding the pads. A G-band variable gain low-noise amplifier featuring the SPST switch shows >50-dB gain control range, with a maximum peak gain of 9.5 dB at 190 GHz and a 3-dB bandwidth from 180 to 203 GHz.

Design of low power single-stage bias current control technique- based DVGA for LTE receivers

In this study, a novel single-stage Digital Variable Gain Amplifier architecture (DVGA) was presented for Long Time Evolution (LTE) receivers. The proposed DVGA combines two transimpedance amplifiers, a transconductance amplifier and a novel digitally controlled current. Using a digital control block, an auxiliary pair to retain a constant current density enabled changing the gain. The Heuristic Method was used to optimize the proposed circuit performance for a high gain, low noise and low power consumption. This circuit was simulated using device-level description of TSMC 0.18 µm CMOS process. The VGA achieved 59 dB gain control range, 171 MHz bandwidth, 11.5 dBm third-order input-intercept point as a minimum gain and below 19 dB noise figure as a maximum gain which makes it convenient for LTE receivers. For maximum gain, The Total Harmonic Distortion (THD) is less than -62 dB. The fully differential VGA has a low THD which it represents a key performance satisfying the LTE system application requirements. The overall power consumption of the circuit is 0.35 mW for ± 0.9 V power supply. This paper also dealt with the prediction of optimized DVGA performances for the upcoming CMOS nanoprocess using the robust Bisquare Weights (BW) method for 16 to 10 nm process nodes. The behavior of the optimized DVGA performances with process scaling was detailed.

A K-Band Dual-Mode Common Gate Cross-Summing VG-LNA With Low Phase Variation

This brief presents a variable-gain low-noise amplifier (VG-LNA) with a common gate (CG) cross-summing configuration, which is fabricated using a 65-nm RF CMOS process. It has a wide gain control range as well as a high input 1 dB gain compression point (IP1dB) at high-gain by introducing a split common-gate transistor (SCGT) technique. In addition, output phase compensation is achieved by adopting a tuning capacitor at the cascode node. This LNA is designed as 2-stage cascode, and the area excluding the pad is 0.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It consumes 25.2 mW with a 1.2-V power supply. It shows a gain of 25 dB and a noise figure of 3.4 dB at 22 GHz. The measured minimum IP1dB is -27.5 dBm, and the root-mean-square phase error is 0.34° over the gain control range of 14 dB at 22 GHz.

A 3.7–43.7-GHz Low-Power Consumption Variable Gain Distributed Amplifier in 90-nm CMOS

A variable gain distributed amplifier (VGDA) for the Rx path of ultrawideband phased-array system is implemented in 90-nm CMOS process and presented in this letter. In order to achieve high gain and wideband with relative low dc power dissipation (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc</sub> ), the combination of the conventional distributed amplifier (CDA) and the cascaded single-stage distributed amplifier (CSSDA) is utilized to the circuit. Moreover, the active variable termination resistor (AVTR) is adopted to adjust the flatness of gain. According to the experimental results, the proposed VGDA achieves a 21-dB peak gain with a 40-GHz 3-dB bandwidth (3.7-43.7 GHz), 18-dB gain control range (GCR), and 16° maximum phase variation.

A 40 MHz 70 dB Gain Variable Gain Amplifier Design Using the gm/ID Design Method

This paper addresses the design and post-fabrication measurements of a 40 MHz CMOS Variable Gain Amplifier (VGA) with a 0 to 70 dB gain control range, using the gm/ID design methodology. The VGA architecture is based on a differential pair stage with an automatic continuous-time offset cancellation circuitry, providing an input offset voltage tolerance up to 50 mV. The 3-stage VGA was designed and fabricated through MOSIS service in an IBM 0.18 μm CMOS process. The VGA dissipates 2.6 mA from a 1.8 V supply, with 34,840 μm2 circuit area, excluding bond-pads.

2.4-GHz CMOS Bluetooth RF Receiver With Improved IM2 Distortion Tolerance

A low-power CMOS sliding-IF RF receiver is presented for Bluetooth Low Energy (BLE) applications. It comprises an LNA, RF mixer, transconductance ( $g_{m}$ ) stage, IF mixer, transimpedance amplifier (TIA), and LO generation block. We present a comprehensive analysis of the second-order intermodulation (IM2) distortion that is induced by an in-band orthogonal frequency-division modulation (OFDM) blocker and its effects on the receiver input sensitivity. Based on the analysis, an in-band two-tone blocker tolerance test procedure is proposed, and an IM2 calibration circuit to enhance the receiver’s IM2 tolerance is presented. Furthermore, a conflict issue in the co-optimization of IM2 calibration at the IF mixer stage and dc offset calibration at the subsequent baseband amplifier stage is alleviated. This is achieved by employing a body bias control method for the dc offset calibration and a gate bias control method for the IM2 calibration. A BLE RF receiver integrated circuit was fabricated in a 65-nm RF CMOS process. Dissipating 3.55 mW from a 1-V supply, it achieves a gain control range from +2 to +62 dB, a minimum noise figure of 3 dB, and an out-of-band (OOB) single-tone blocker tolerance level of −10 dBm. Measurement results demonstrate that the proposed IM2 calibration circuit significantly improves the in-band two-tone blocker tolerance level by 7–12 dB, achieving its range from −41 to −31 dBm.