Gate Control Research Articles

Synthesis and Characterization of Stimuli-Responsive Polymer Brushes in Nanofluidic Channels.

Nanochannels with controllable gating behavior are attractive features in a wide range of nanofluidic applications including viral detection, particle sorting, and flow regulation. Here, we use selective sidewall functionalization of nanochannels with a polyelectrolyte brush to investigate the channel gating response to variations in solution pH and ionic strength. The conformational and structural changes of the interfacial brush layer within the channels are interrogated by specular and off-specular neutron reflectometry. Simultaneous fits of the specular and off-specular signals, using a dynamical theory model and a fitting optimization protocol, enable detailed characterization of the brush conformations and corresponding channel geometry under different solution conditions. Our results indicate a collapsed brush state under basic pH, equivalent to an open gate, and an expanded brush state representing a partially closed gate upon decreasing the pH and salt concentration. These findings open new possibilities in noninvasive in situ characterization of tunable nanofluidics and lab-on-chip devices with advanced designs and improved functionality.

Flow Prediction of a Measurement and Control Gate Based on an Optimized Back Propagation Neural Network

The measurement and control gate, as a new type of measurement and control equipment, has been widely used for water quantity control in irrigation areas. However, there is a lack of methods for calibrating the flow inside the measurement box at present. This paper establishes a flow prediction model based on a back propagation (BP) neural network and its optimization algorithm by using 450 sets of sample data obtained from the indoor gate overflow test and verified the effectiveness and accuracy of the prediction model by using another 205 sets of sample data. The results show that the gate flow prediction model based on a BP neural network and its optimization algorithm has self-adaptability to different flow patterns, and its prediction accuracy is significantly higher than that of the traditional water measurement method. Compared to the unoptimized BP model, the BP model optimized by the genetic algorithm (GA) or particle swarm optimization (PSO) has higher prediction accuracy and better error distribution. Both GA and PSO algorithms can be used to optimize the initial weights and thresholds of the BP flow prediction model. However, by comprehensively analyzing the prediction accuracy, error distribution, and running time, the PSO algorithm has better optimization performance compared to the GA algorithm. The prediction model can provide a reference for flow rate calibration and the anomaly rejection of measurement and control gates in the irrigation area.

Dissecting the Interplay between Organic Charge-Modulated Field-Effect Transistors and Field-Effect Transistors through Interface Control Engineering.

Organic charge-modulated field-effect transistors (OCMFETs) have garnered significant interest as sensing platforms for diverse applications that include biomaterials and chemical sensors owing to their distinct operational principles. This study aims to improve the understanding of driving mechanisms in OCMFETs and optimize their device performance by investigating the correlation between organic field-effect transistors (OFETs) and OCMFETs. By introducing self-assembled monolayers (SAMs) with different functional groups on the AlOx gate dielectric surface, we explored the impact of the surface characteristics on the electrical behavior of both devices. Our results indicate that the dipole moment of the dielectric surface is a critical control variable in the performance correlation between OFET and OCMFET devices, as it directly impacts the generation of the induced floating gate voltage through the control gate voltage. The insights obtained from this study contribute to the understanding of the factors affecting OCMFET performance and emphasize their potential as platforms for diverse sensing systems.

Design of an Advanced Intelligent Automatic Railway Gate Controller System for Avoiding Accidents at Crossing Points Using Verilog HDL

Design of an Advanced Intelligent Automatic Railway Gate Controller System for Avoiding Accidents at Crossing Points Using Verilog HDL

Low thermal budget V/Al/Mo/Au ohmic contacts for improved performance of AlGaN/GaN MIS-HEMTs

We report on the highly improved performance of Al2O3/AlGaN/GaN MIS-HEMTs using a V/Al/Mo/Au metal stack as ohmic electrodes. Transfer length method test structures using a V/Al/Mo/Au metal stack annealed at a temperature of 660 °C revealed highly linear current–voltage curves and smooth surface morphology. Compared with reference MIS-HEMTs using Ti/Al/Mo/Au annealed at the standard rapid thermal annealing temperature of 880 °C, V-based devices exhibited less hysteresis of transfer curves and showed higher gate controllability of the drain current, suggesting a highly improved Al2O3/AlGaN interface. Measurements and analyses of capacitance–voltage characteristics of corresponding MIS-capacitors corroborated these findings. The V-based ohmic contact could open new avenues towards enhanced GaN-based MIS-HEMTs performance.

Inkjet‐Printed, Wafer‐Scale Organic Schottky‐Gate Transistors toward Single‐Battery‐Driven Integrated Logic

AbstractOrganic field‐effect transistors switched by insulated gates are the most essential building blocks, while usually plagued with degraded gate control arising from complicated dielectric engineering. Subsequently, the resulting large supply voltage and power consumption remain an essential issue for portable electronics driven by a single battery of only 1.5 V. Herein, wafer‐scale organic Schottky‐gate transistor arrays using inkjet‐printed few‐layer organic semiconducting crystals are reported. The transistors exhibit steep switching characteristics with an average subthreshold swing of 55 mV per dec and high signal amplification efficiency over 45 S A‐1, attributed to efficient Schottky gating and enhanced charge injection. Thereafter, high‐gain inverters are successfully demonstrated with an ultralow power consumption of only 800 pW; also, they are integrated as 1 V driven sequential logic circuits. A coplanar double‐gate geometry is also introduced for low‐voltage, single‐device AND logic. Therefore, the work opens new avenues toward the sustainable advancement in single‐battery‐driven, ultralow‐power organic electronics.

KAJIAN PENILAIAN KINERJA SUNGAI BEKASI

The Bekasi River is part of the Ciliwung-Cisadane River Region. The Bekasi River is an order 1 river from the Bekasi watershed which consists of 3 rivers, namely the Cileungsi River, Cikeas River and Bekasi River. The Bekasi River passes through Bekasi Regency. To determine the performance of a river, it is necessary to evaluate the physical condition and function of a river system, in accordance with the mandate from the Circular Letter of the Director General of Water Resources, Ministry of Public Works and Public Housing No. 05/SE/D/2016 dated 9 June 2016 concerning Guidelines for the Operation and Maintenance of River Infrastructure and River Maintenance. Assessment of the components of the Bekasi River facility based on Circular Letter Number 05/SE/D/2016 includes riverbeds, river banks, river banks, and river riparian areas. Assessment of the Bekasi River infrastructure components based on Circular Letter Number 05/SE/D/2016 includes river embankments, revetments, groves, flood spillways, flow control gates, flood pumps, rubber weirs, retention ponds, groundssill, inspection roads, H3 monitoring post buildings, Operation and Maintenance support buildings (laboratory, workshop, etc.), equipment infrastructure (heavy equipment, Operation and Maintenance vehicles), and information and communication equipment. The performance value of the Bekasi River condition is 77.85% and the performance value of the Bekasi River infrastructure is 79.30% so that the performance value of the Bekasi River is 78.58% which requires a type of Preventive maintenance.

Parametric Simulation Study of Control Coefficients on the On-Off Current Ratio of Single-Walled Carbon Nanotube Field Effect Transistor

As the semiconductor business faces increasing technical and financial challenges, it is crucial to assess and analyze new ideas thoroughly. The unique properties of carbon nanotubes make them a promising material for applications in micro and nanoelectronics. The study focused on simulating the impact of control coefficients (gate and drain) on device characteristics. The simulation results were then analyzed using existing models. This research focused on studying the ION/IOFF ratio by varying the thickness and diameter of the nanotubes. The control coefficients have been observed to have an impact on the current levels. Increasing the drain control coefficient negatively impacts device performance, while raising the gate control coefficient positively affects the current ratio.

Enhancing Gating Performance in Organic Molecular Field-Effect Transistors by Introducing Polar Azulene Components.

Organic molecular field-effect transistors (FETs) are promising building components for future electronic circuits. Efficient control of charge transport properties is one key issue in the design of organic molecular FETs. In this study, we propose a redesign of a naphthalene-based FET by introducing two azulene components in opposite dipole moment directions. Using density functional theory combined with non-equilibrium Green's function, the simulated electronic transport characteristics reveal that the introduction of polar azulene components effectively narrows the frontier molecular orbitals gap, leading to an increase in the ON-state current. Meanwhile, the OFF-state current is significantly suppressed by highly localizing the dominant electronic transport channel. As a result, improved gate controllability is achieved with a higher ON-OFF current ratio, which is nearly seven times higher than that of the naphthalene-based FET device. These findings provide theoretical directions for future design of organic molecular FET devices with enhanced gating regulation efficiency.

A hierarchical control framework for alleviating network traffic bottleneck congestion using vehicle trajectory data

Traffic bottlenecks significantly influence the operation efficiency of large-scale road networks. Developing advanced control strategies for bottleneck optimization is a cost-efficient and critical way to deal with network congestion. However, the state-of-the-art studies on network congestion control focus on the topology level, which may fail to relieve congestion by addressing the root cause of bottleneck. This study proposed a hierarchical control framework for alleviating network traffic bottleneck congestion using vehicle trajectory data. First, the bottleneck-related sub-network (BRS) was identified by tracing vehicle trajectories upstream and downstream of the bottleneck based on the traffic flow propagation. Then, a hierarchical control framework was proposed for BRS optimization. Specifically, in the outer layer, i.e., the gating control layer, the multigated intersections in BRS were controlled via a multimemory deep Q-network approach to optimize the network traffic distribution. In the inner layer, i.e., the coordinated control layer, local intersection controllers were coordinated by adjusting the dynamic input and output streams of the bottleneck under the guidance of the outer layer controller, which helps balance the traffic pressure within BRS and avoids congestion transferring in the network. Both simulation and field experiments were conducted to verify the performance of the proposed hierarchical framework. Results reveal that the framework can effectively relieve network traffic congestion with decreased queue length and travel time.

Dynamic Management of Urban Coastal Traffic and Port Access Control

Urban traffic congestion and vehicle/passenger port recurring delays are major obstacles of coastal urban area sustainability. Most research in coastal urban road management has focused on congestion detection without the effective integration of the dynamic interactions with port queueing systems. For securing coastal city environmental, social and economic efficiency, this paper develops and tests a dynamic urban coastal traffic and port management system. The integrated system controls traffic and port gates’ operations based on ITS/C-ITS methodologies. The system integrates dynamic models for congestion detection, using ANN and a parameterized model, on a coastal urban road network that leads to a city port and identifies optimal solutions for road traffic and port queuing gate control. The system communicates with users via connected vehicles and VMS. The system was tested in a coastal urban road leading to Patras Southern Port, Greece, and at port control gates. Field and simulation data were used to assess system performance and social–environmental impacts. The results reveal that the system’s application offers benefits to the individual driver moving towards the Port to board a ship (gaining at least 7 min and consuming 0.306 L less fuel) as well as to society (39.72% increase in traffic safety) and environment (1,445,132 g CO2 emission reduction).

Demonstration of Germanium Vertical Gate-All-Around Field-Effect Transistors Featured by Self-Aligned High-κ Metal Gates with Record High Performance.

A special Ge nanowire/nanosheet (NW/NS) p-type vertical sandwich gate-all-around (GAA) field-effect transistor (FET) (Ge NW/NS pVSAFET) with self-aligned high-κ metal gates (HKMGs) is proposed. The Ge pVSAFETs were fabricated by high-quality GeSi/Ge epitaxy, an exclusively developed self-limiting isotropic quasi atomic layer etching (qALE) of Ge selective to both GeSi and the (111) plane, top-drain implantation, and ozone postoxidation (OPO) channel passivation. The Ge pVSAFETs, which have hourglass-shaped (111) channels with the smallest size range from 5 to 20 nm formed by qALE, have reached a record high Ion of ∼291 μA/μm and exhibited good short channel effects (SCEs) control. The integration flow is compatible with mainstream CMOS processes, and Ge pVSAFETs with precise control of gate lengths/channel sizes were obtained.

Digital-logic assessment of junctionless twin gate trench channel (JL-TGTC) MOSFET for memory circuit applications

In this paper, Junctionless Twin Gate Trench Channel (JL-TGTC) MOSFET with individual gate control is realized. The device gives full functionality of 2-input digital ‘AND’ and ‘NAND’ logics. The simulation depicts the results in the form of various parameters such as cutoff current, transfer characteristics, and potential profiles. All the simulations regarding device structure and functionality are done on TCAD. This new type of MOS device has improved applicability in low-voltage digital electronics such as sequential circuits etc.

Reconfigurable Logic‐In‐Memory Cell Comprising Triple‐Gated Feedback Field‐Effect Transistors

AbstractA reconfigurable logic‐in‐memory (R‐LIM) cell performs logic‐in‐memory functions as well as reconfigurable logic gates. The R‐LIM cell is constructed with triple‐gated (TG) feedback field‐effect transistors (FBFETs) that are reconfigured in n‐channel or p‐channel modes via electrostatic doping. Each TG FBFET has one control gate electrode and two program‐gate electrodes that determine the channel mode. Their reconfigurability enables the symmetrical operation of the n‐channel and p‐channel modes through an on‐current ratio of 1:04. Furthermore, the R‐LIM cell performs eight Boolean logic operations, storing the logic outputs for ≈100 s under zero‐bias conditions. The R‐LIM cell is useful for developing in‐memory computing systems with high energy efficiency and functional logic.

Birefringence after Tellurium Nanosheets and Copper Intercalation

Symmetry-deficient two-dimensional (2D) layered materials induce a highly anisotropic optical response due to the anisotropy in their crystal structure, facilitating their application in polarized nanodevices. Intercalation is a new way to tune the optoelectronic properties of materials by inserting guest atoms into layered host materials, and 2D layered structures stacked with van der Waals gaps are a prerequisite for this phase of the technique. In this paper, 2D tellurium nanosheets were synthesized with a hydrothermal method, and copper atoms were inserted with a wet chemical method. The widening of the crystal plane spacing proves the introduction of copper atoms, and polarization−related second-harmonic-generation (SHG) studies reveal the intrinsic anisotropic modes of the two samples, and birefringent properties are found with polarizing light microscopy. We further investigated the electrical properties of the samples, and the embedding of the copper atoms caused the samples to exhibit higher currents, but their devices lost the gate control effect.

Memtransistor-like operation of devices made by graphene/h-BN/MoS2 van der Waals heterostructure

We present the fabrication and characterization of a flash memory device based on a van der Waals (vdW) heterostructure comprising graphene (Gr), hexagonal boron nitride (h-BN), and molybdenum disulfide (MoS2). The device exhibits versatile functionalities and demonstrates memtransistor-like behavior, making it a promising candidate for synaptic devices and neuromorphic computing. The Gr/h-BN/MoS2 heterostructure allows for the manipulation of charge concentration in the floating gate (FG) through control gate voltage (VBG), resulting in conductance switching. Moreover, the overlap structure of the FG and source-drain electrodes enables memtransistor-like operations, where the writing processes rely on the source-drain voltage (VDS). By varying carrier storage concentrations in the Gr-FG, multiple memory states can be achieved, offering analog information processing capabilities. In addition, the combination of dual-input functionality allows for the identification of a substantial on/off ratio even when utilizing a lower reading VDS, consequently strengthening the dependability of the memory state. Our work showcases the great potential of the Gr/h-BN/MoS2 heterostructure for advanced nanoelectronics, providing a platform for the development of computing architectures and neuromorphic systems.

Bond wire lift-off detection by gate voltage waveform in IGBT turn-off process enhanced by digital gate control

This paper presents a new detection method of bond wire lift-off in Insulated Gate Bipolar Transistor (IGBT) power module. The bond wire lift-off is a major failure mode in power cycle degradation of the IGBT module, and many monitoring methods have been proposed and demonstrated for safety operation of power electronics systems in the previous works. In this study, we focus on the gate voltage waveform as an indicator to detect wire-lift for a simple and straightforward detection method. Due to the increase in parasitic inductance caused by bond wire lift-off, the turn-off switching waveform becomes modulated. The digital gate control (DGC) was employed to control the switching behavior to obtain precision for low-noise and high-performance. Furthermore, the DGC 2-step vector control (2-sVC) can enhance the sensitivity of bond wire lift-off failure detection by gate voltage waveform change. As feature quantities, the gate voltage spike peak, its amplitude and the timing shift were measured at various operating conditions. The DGC obtained larger feature quantities compared with conventional gate control. In particular, high-current conditions were found to be more favorable for achieving high sensitivity due to the high die/dt. From these results, the DGC is effective to achieve both the high sensitivity to detect bond wire lift-off by gate voltage waveform and maintaining the best switching performance.

Junction temperature balance control for paralleled SiC MOSFETs based on active gate control

Power devices operating in parallel often experience thermal stress imbalances, which can lead to failures, especially in silicon carbide (SiC) MOSFETs. To enhance their reliability, controlling the junction temperature becomes crucial. Existing research focuses on addressing current imbalances in parallel devices, neglecting the issue of junction temperature imbalances. It is worth noting that even with balanced currents, the junction temperatures may still vary. To address this challenge, we propose a novel active gate control-based method for achieving junction temperature balance in parallel devices. This method not only ensures junction temperature balance but also effectively suppresses dynamic current peaks. To validate the effectiveness of our approach, we conducted experimental tests on a BUCK converter utilizing two parallel SiC MOSFETs. The experimental results demonstrate the achievement of junction temperature balance and excellent suppression of dynamic current peaks through the proposed method.

Ultra Sensitive Breast Cancer Cell Lines Detection Using Dual Nanocavities Engraved Junctionless FET.

This article reports breast cancer cell lines (Hs578T, MDA-MB-231, MCF-7, and T47D) and healthy breast cells (MCF-10A) detection based on the modulation of its electrical properties by deploying dual nanocavity engraved junctionless FET. The device has a dual gate to enhance gate control and has two nanocavities etched under both gates for breast cancer cell lines immobilization. As the cancer cells are immobilized in the engraved nanocavities, which were earlier filled with air, the dielectric constant of the nanocavities changes. This results in the modulation of the device's electrical parameters. This electrical parameters modulation is then calibrated to detect the breast cancer cell lines. The reported device demonstrates a higher sensitivity toward the detection of breast cancer cells. The JLFET device optimization is done for improving the performance by optimizing the nanocavity thickness and the SiO2 oxide length. The variation in the dielectric property of cell lines plays a key role in the detection technique of the reported biosensor. The sensitivity of the JLFET biosensor is analyzed in terms of ∆VTH, ∆ION, ∆gm , and ∆SS . The reported biosensor shows the maximum sensitivity for T47D ( κ = 32 ) breast cancer cell line with ∆VTH = 0.800 V, ∆ION = 0.165 mA/μm, ∆gm = 0.296 mA/V-μm , and ∆SS = 5.41 mV/decade. Moreover, the effect of variation in the occupancy of the cavity by the immobilized cell lines has also been studied and analyzed. With increased cavity occupancy the variation in the device performance parameter enhances Further, the sensitivity of the proposed biosensor is compared with the existing biosensors and it is reported to be highly sensitive as compared to the existing biosensors. Hence, the device can be utilized for array based screening of cell lines of breast cancer and diagnosis with the benefit of easier fabrication and cost effectiveness of the device.

Design and Analysis of Electrical Characteristics of 14nm SOI-based Trigate Gaussian Channel Junctionless FinFET

Planar MOSFETs are reaching their physical limits. To overcome the limitations and improve channel gate control, FinFET technology, which uses many gate devices, is a superior choice while lowering the size of planar MOSFETs even further. In this paper, 14nm Silicon-On-Insulator-based Trigate Gaussian Channel Junctionless FinFET is presented. The gate length of 14nm is considered along with an Equivalent Oxide Thickness of 1nm, 5nm as fin width, and the work function of the gate metal is 4.75eV. The device architecture has a non-uniform doping profile (Gaussian distribution) across the fin’s thickness. It is devised to address the effects of Random Dopant Fluctuations such as channel mobility degradation in Junctionless FinFET based devices. The impact of fin height (Fh), gate dielectric and spacer dielectric on the Drain Induced Barrier Lowering, Subthreshold Swing, drain current of GC-JLFinFET is analyzed. The results show that the Ion=101.5μA/μm and Ion/Ioff is 3.2×107 are obtained for the proposed device structure compared to the existing structure, which has Ion/Ioff of 1.1x107. Furthermore, the proposed design shows better efficiency in short channel characteristics, namely DIBL=25.3 mV/V, Subthreshold Swing=63.88 mV/dec and Transconductance =3.621×105 S/μm. Thus the Gaussian Channel-based FinFET architecture can provide optimum results for Junctionless-based FinFET devices.