Digital-logic assessment of junctionless twin gate trench channel (JL-TGTC) MOSFET for memory circuit applications

Ajay Kumar,Neha Gupta,Aditya Jain,Rajeev Gupta,Bharat Choudhary,Kaushal Kumar,Amit Kumar Goyal,Yehia Massoud

doi:10.1016/j.memori.2023.100087

Digital-logic assessment of junctionless twin gate trench channel (JL-TGTC) MOSFET for memory circuit applications

Ajay Kumar, Neha Gupta + Show 6 more

Open Access

https://doi.org/10.1016/j.memori.2023.100087

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Journal: Memories - Materials, Devices, Circuits and Systems	Publication Date: Oct 11, 2023
Citations: 1	License type: cc-by-nc-nd

Affiliation: Jaypee Institute of Information Technology, JRE Group of Institutions, Symbiosis International University, University of Petroleum and Energy Studies, Malaviya National Institute of Technology Jaipur, Graphic Era University, King Abdullah University of Science and Technology

#Channel MOSFET #Sequential Circuits + Show 8 more

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Abstract

In this paper, Junctionless Twin Gate Trench Channel (JL-TGTC) MOSFET with individual gate control is realized. The device gives full functionality of 2-input digital ‘AND’ and ‘NAND’ logics. The simulation depicts the results in the form of various parameters such as cutoff current, transfer characteristics, and potential profiles. All the simulations regarding device structure and functionality are done on TCAD. This new type of MOS device has improved applicability in low-voltage digital electronics such as sequential circuits etc.

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