Gate Voltage Control Research Articles

Niobium Dayem nano-bridge Josephson gate-controlled transistors

We report on the realization of Nb-based all-metallic Dayem nano-bridge gate-controlled transistors (Nb-GCTs). These Josephson devices operate up to a temperature of ∼3 K and exhibit full suppression of the supercurrent thanks to the application of a control gate voltage. The dependence of the kinetic inductance and of the transconductance on gate voltage promises a performance already on par with so far realized metallic Josephson transistors and leads us to foresee the implementation of a superconducting digital logic based on the Nb-GCT. We conclude by showing the practical realization of a scheme implementing an all-metallic gate-tunable half-wave rectifier to be used for either superconducting electronics or photon detection applications.

Tunable compression of THz chirped pulses using a helical graphene ribbon-loaded hollow-core waveguide.

Pulse shaping is important for communications, spectroscopy, and other applications that require high peak power and pulsed operation, such as radar systems. Unfortunately, pulse shaping remains largely elusive for terahertz (THz) frequencies. To address this void, a comprehensive study on the dispersion tunability properties of THz chirped pulses traveling through a dielectric-lined hollow-core waveguide loaded with a helical graphene ribbon is presented. It is demonstrated that there is an optimal compression waveguide length over which THz chirped pulses reach the maximum compression. The optimal length is dependent on the chirp pulse duration. It is shown that by applying an electrostatic controlling gate voltage (Vg) of 0 and 30 V on the helical graphene ribbon, the temporal input pulses of width 8 and 12 ps, propagating through two different lengths, can be tuned by 5.9% and 8%, respectively, in the frequency range of 2.15-2.28 THz.

Four-terminal polycrystalline Ge1−xSnx thin-film transistors using copper-induced crystallization on glass substrates and their application to enhancement/depletion inverters

Polycrystalline germanium–tin (Ge1−xSnx) thin films with a thickness of 15 nm were grown at 500 °C using Cu-induced crystallization. The films were applied to fabricate four-terminal (4T) thin-film transistors (TFTs) on a glass substrate. The top gate (TG) was fabricated from 30 nm thick SiO2, while the bottom gate (BG) consisted of a double layer of HfO2 and SiO2 with a capacitance equivalent thickness of 16 nm. Aluminum-induced lateral metallization of the source and drain (SD) was implemented to decrease the parasitic resistance of the SD. The Ion/Ioff of the double gate approximately corresponded to 1 × 104. Furthermore, 4T poly-Ge1−xSnx TFTs operated with a field-effect mobility of 20 cm2 V−1 s−1 for the TG drive and 12 cm2 V−1 s−1 for the BG drive at a control gate voltage of 0 V in both cases. A p-channel enhancement/depletion inverter was validated based on the precise control of threshold voltage using a control gate.

New low power differential VCO circuit designs with active load and IMOS varactor

In this paper, low power differential voltage-controlled oscillators (VCOs) have been reported utilizing the active load and inversion mode MOSFET (IMOS) varactor in the delay stages. VCO circuits operation is based on two NOR gates in differential mode, variations in gate control voltage of the NMOS/PMOS active load, and the varactor control voltage of IMOS. For VCO based on NMOS active load, variations in gate control voltage from 1.0 V to 2.0 V exhibit frequency variations from 6.687 GHz to 6.395 GHz. For VCO based on PMOS active load, variations in gate control voltage of PMOS active load from −0.5 V to 0.5 V provide frequency variations from 5.726 GHz to 6.142 GHz. For VCO based on IMOS varactor, variations in varactor control voltage of IMOS from 1.0 V to 2.0 V shows variations in output frequency from 3.796 GHz to 4.499 GHz with power dissipation of 2.06 mW. Proposed VCOs shows a phase noise of −76.20 dBc/Hz@1MHz for NMOS active load, −73.42 dBc/Hz@1MHz for PMOS active load and −75.63 dBc/Hz@1MHz for IMOS varactor load and the figure of merit (FoM) for the VCOs are −149.43 dBc/Hz, −145.58 dBc/Hz and −145.17 dBc/Hz, respectively.

Gate-Voltage Control of Quantum Yield in Monolayer Transition-Metal Dichalcogenide

Two-dimensional transition metal dichalcogenide (2D-TMD) monolayers, which reveal remarkable semiconductor properties, are the subject of active experimental research.Recently it has been shown experimentally that quantum yield in MoS2 and WSe2 monoatomic layers can reach values close to unity when electrostatic doping makes them intrinsic semiconductors. However, the available theoretical description does not give an understanding of the physical mechanisms underlying in the gate voltage control of quantum yield.This work is an attempt to propose a consistent semi-phenomenological theory of photo-induced charge carriers relaxation in 2D-TMDs, which allows obtaining an analytical dependence of the quantum yield on the voltage applied to the FET gate. We consider a standard experimental situation, when the 2D-TMD monolayer and the metal gate are plates of a flat capacitor, and the capacitor charge is proportional to the gate voltage. The dependences of the TMD monolayers quantum yield on the gate voltage and the carrier generation rate have been calculated for the cases of the prevailing recombination of free electrons and holes (radiative and non-radiative Auger recombination) and recombination of excitons (radiative and Auger recombination). In both cases analytical expressions were derived for the dependence of quantum yield on the gate voltage and photo-induced carriers generation rate at a fixed gate voltage. Quantitative agreement with experiment allows concluding about the relevance of the proposed theoretical model for the description of carriers photo-generation and recombination in 2D-TMD monolayers. Obtained results demonstrate the possibilities of 2D-TMD quantum yield control by the gate voltage and indicate that 2D-TMDs are promising candidates for modern optoelectronics devices.

Giant magnetoresistance and dual spin filtering effect in ferromagnetic 6,6,12/γ-graphyne zigzag nanoribbon lateral heterojunction.

Based on non-equilibrium Green's function combined with density functional theory (NEGF-DFT), we investigate the spin dependent transport in the ferromagnetic 6,6,12/γ-graphyne zigzag nanoribbon (GYZNR) heterojunction under different magnetic configurations. It is found that, at low bias ([-0.05, 0.1] V), the junction presents metallic transport with negligible spin polarization in parallel configuration (PC) while it behaves as an insulator in anti-parallel configuration (APC), which results in giant magnetoresistance. Interestingly, when we increase the bias voltage beyond [-0.05, 0.1] V, dual spin filtering characterized by electron transport of different spin channels under different polarity of bias is observed in APC but not in PC. All these findings are understood from the symmetry matching of wave functions in two nanoribbons at equilibrium or finite bias. Furthermore, dual spin filtering can also be achieved in PC by applying a gate voltage on the central interface region, which arises from the shift of different single spin channel of the central gate region into the bias window at a different polarity of the gate voltage. Thus, our work demonstrates the great potential of the 6,6,12/γ-GYZNR heterojunction as a multi-functional device and its great perspectives in carbon-based nanoelectronics and spintronics.

A simple method for preparing a TiO2-based back-gate controlled N-channel MSM–IGFET UV photodetector

An N-channel IGFET UV photodetector was fabricated by means of the ALD, calcination in air and mask plating of electrodes. Such device demonstrates properties of controllable gate voltage and high gain (2–3 × 104).

Theoretical Study on Spin-Selective Coherent Electron Transfer in a Quantum Dot Array

Recently, we proposed the spin-selective coherent electron transfer in a silicon-quantum-dot array. It requires temporal tuning of two pulses of an oscillating magnetic field and gate voltage control. This paper proposes a simpler method that requires a single pulse of oscillating magnetic field and gate voltage control. We examined the robustness of the control against the error in the pulse amplitude and the effect of the excited states relaxation to the control efficiency. In addition, we propose a novel control method based on a shortcuts-to-adiabaticity protocol, which utilizes two pulses but requires temporal control of the pulse amplitude for only one of them. We compared their efficiencies under the effect of realistic pulse amplitude errors and relaxation.

Open-Loop Gate Control for Optimizing the Turn-ON Transition of SiC MOSFETs

This paper presents a novel open-loop gate control of the turn-ON transient for SiC MOSFETs in hard switching conditions. The gate control could reduce the SiC MOSFETs turn-ON gate voltage overshoot and control turn-ON $di/dt$ and $dv/dt$ independently. Because of the high turn-ON speed, SiC MOSFETs bring serious electromagnetic interference (EMI) in the half-bridge topology. A conventional gate driver decreases EMI by increasing the gate resistor, but clearly increasing the turn-ON loss. To address this tradeoff and optimize SiC MOSFETs turn-ON transition, the drain current slope and the drain–source voltage slope are controlled independently by controlling the gate–source voltage profile during the current rise phase and the gate current during the voltage falling phase. In addition, gate voltage overshoot is considered and discussed. By adding a considerably higher gate resistance during the ON-state operation stage, gate voltage overshoot is almost nonexistent while maintaining low turn-ON loss. The experimental verifications of the proposed approach are finally conducted, and the advantages of proposed driver are analyzed and discussed.

Thickness of accumulation layer in amorphous indium-gallium-zinc-oxide thin-film transistors by Kelvin Probe Force Microscopy

In this letter, we measured the thickness of an accumulation layer (dacc) in amorphous Indium-Gallium-Zinc-Oxide thin-film transistors (TFTs) using Kelvin Probe Force Microscopy (KPFM). By scanning the active layer surface from the interface to the back channel, we obtained potential from different thickness profiles, which show the variation of the carrier concentration. It was found that potential followed an exponential decay function from the interface to the back channel. Furthermore, there was a transition point after which the potential changed little. From this potential map, the thickness of the accumulation layer could be considered as the height difference between the transition point and the interface. Meanwhile, by controlling gate voltage (VG) during the KPFM scanning process, we obtained a relationship between dacc and VG. The results indicated that when VG was smaller than threshold voltage (Vth), dacc increased drastically with the increase in VG; after that, dacc was almost independent of VG, indicating that dacc reached a saturation value around 15 nm. This finding gave us a clear physical image about charge distribution in TFT and facilitated the understanding of device physics.

A Simple Closed-Loop Active Gate Voltage Driver for Controlling diC/dt and dvCE/dt in IGBTs

The increase of the switching speed in power semiconductors leads to converters with better efficiency and high power density. On the other hand, fast switching generates some consequences like overshoots and higher switching transient, which provoke electromagnetic interference (EMI). This paper proposes a new closed-loop gate driver to improve switching trajectory in insulated gate bipolar transistors (IGBTs) at the hard switching condition. The proposed closed-loop gate driver is based on an active gate voltage control method, which deals with emitter voltage (VEe) for controlling diC/dt and gets feedback from the output voltage (vCE) in order to control dvCE/dt. The sampled voltage signals modify the profile of the applied gate voltage (vgg). As a result, the desired gate driver (GD) improves the switching transients with minimum switching loss. The operation principle and implementation of the controller in the GD are thoroughly described. It can be observed that the new GD controls both dvCE/dt and diC/dt accurately independent of the variable parameters. The new control method is verified by experimental results. As a current issue, the known trade-off between switching losses and EMI is improved by this simple and effective control method.

Thermoelectric Parameter Modeling of Single-Layer Graphene Considering Carrier Concentration and Mobility With Temperature and Gate Voltage

Single-layer graphene (SLG) sheets can exhibit thermoelectric properties under the control of gate voltage. The controlled factors and regulation mechanism of SLG thermoelectric properties have become research hotspots. In this paper, a SLG thermoelectric parameter model considering carrier concentration and mobility with temperature and gate voltage is proposed. Based on the proposed model, the square resistance ( $R_{\mathrm {s}}$ ) and Seebeck coefficient ( $S$ ) of the SLG are calculated. The results show that the maximum value of $R_{\mathrm {s}}$ decreases from 5.8 $\text{K}\Omega $ to 3.2 $\text{K}\Omega $ at the Dirac voltage when the temperature increases from 100 K to 500 K. A large and stable $S$ can be obtained at high voltages and temperatures. The maximum value of $S$ can reach $161.3~\mu \text{V}$ /K at $T = 500$ K, exhibiting a more obvious thermoelectric characteristic. Simultaneously, the saturation law of the power factor ( $Q$ ) with the change of gate voltage and the amplitude regulation of $Q$ by temperature are obtained. This work can provide a theoretical basis for analyzing the thermoelectric characteristics of SLG.

Low Residual Carrier Concentration and High Mobility in 2D Semiconducting Bi2O2Se.

The air-stable and high-mobility two-dimensional (2D) Bi2O2Se semiconductor has emerged as a promising alternative that is complementary to graphene, MoS2, and black phosphorus for next-generation digital applications. However, the room-temperature residual charge carrier concentration of 2D Bi2O2Se nanoplates synthesized so far is as high as about 1019-1020 cm-3, which results in a poor electrostatic gate control and unsuitable threshold voltage, detrimental to the fabrication of high-performance low-power devices. Here, we first present a facile approach for synthesizing 2D Bi2O2Se single crystals with ultralow carrier concentration of ∼1016 cm-3 and high Hall mobility up to 410 cm2 V-1 s-1 simultaneously at room temperature. With optimized conditions, these high-mobility and low-carrier-concentration 2D Bi2O2Se nanoplates with domain sizes greater than 250 μm and thicknesses down to 4 layers (∼2.5 nm) were readily grown by using Se and Bi2O3 powders as coevaporation sources in a dual heating zone chemical vapor deposition (CVD) system. High-quality 2D Bi2O2Se crystals were fabricated into high-performance and low-power transistors, showing excellent current modulation of >106, robust current saturation, and low threshold voltage of -0.4 V. All these features suggest 2D Bi2O2Se as an alternative option for high-performance low-power digital applications.

Fully Printed Flexible Dual-Gate Carbon Nanotube Thin-Film Transistors with Tunable Ambipolar Characteristics for Complementary Logic Circuits

Semiconducting single-wall carbon nanotubes (sSWCNTs) have been widely used as the channel material for high-performance printed flexible thin-film transistors (TFTs). Due to the absorption of moisture and oxygen in air, the printed sSWCNT TFTs generally exhibit p-type characteristics only. In this paper, we report fully printed dual-gate sSWCNT TFTs that exhibit almost symmetric ambipolar characteristics. With the applied control gate voltage varying from -60 to +60 V, a threshold voltage tuning range of 27 V is achieved, allowing the device to be effectively tuned into either predominantly p-type or predominantly n-type. The tunable ambipolar characteristics are found to be very stable over a long period of time (4 months). By integrating two printed dual-gate TFTs biased with different control gate voltages, a complementary metal oxide semiconductor inverter with close to rail-to-rail output voltage swing is demonstrated. The use of a dual-gate structure for achieving n-type printed carbon nanotube TFTs is much more controllable and repeatable compared to other methods such as chemical doping. Our work shows the feasibility of implementing more sophisticated complementary logic circuits using printed flexible carbon nanotube transistors.

Tuning Rashba Spin-Orbit Coupling in Gated Multilayer InSe.

Manipulating the electron spin with the aid of spin-orbit coupling (SOC) is an indispensable element of spintronics. Electrostatically gating a material with strong SOC results in an effective magnetic field which can in turn be used to govern the electron spin. In this work, we report the existence and electrostatic tunability of Rashba SOC in multilayer InSe. We observed a gate-voltage-tuned crossover from weak localization (WL) to weak antilocalization (WAL) effect in quantum transport studies of InSe, which suggests an increasing SOC strength. Quantitative analyses of magneto-transport studies and energy band diagram calculations provide strong evidence for the predominance of Rashba SOC in electrostatically gated InSe. Furthermore, we attribute the tendency of the SOC strength to saturate at high gate voltages to the increased electronic density of states-induced saturation of the electric field experienced by the electrons in the InSe layer. This explanation of nonlinear gate voltage control of Rashba SOC can be generalized to other electrostatically gated semiconductor nanomaterials in which a similar tendency of spin-orbit length saturation was observed (e.g., nanowire field effect transistors), and is thus of broad implications in spintronics. Identifying and controlling the Rashba SOC in InSe may serve pivotally in devising III-VI semiconductor-based spintronic devices in the future.

Direct observation of the orbital spin Kondo effect in gallium arsenide quantum dots

Besides the spin Kondo effect, other degrees of freedom can give rise to the pseudospin Kondo effect. We report a direct observation of the orbital spin Kondo effect in a series-coupled gallium arsenide (GaAs) double quantum dot device where orbital degrees act as pseudospin. Electron occupation in both dots induces a pseudospin Kondo effect. In a region of one net spin impurity, complete spectra with three resonance peaks are observed. Furthermore, we observe a pseudo-Zeeman effect and demonstrate its electrical controllability for the artificial pseudospin in this orbital spin Kondo process via gate voltage control. The fourfold degeneracy point is realized at a specific value supplemented by spin degeneracy, indicating a transition from the SU(2) to the SU(4) Kondo effect.

Linear CMOS power amplifier using continuous gate voltage control

AbstractIn this article, an linearization technique using a gate voltage adaptation of a common gate stage for a cascode CMOS power amplifier (PA) is presented. The tracking of minimum in‐band third‐order intermodulation distortion by controlling with respect to instantaneous power level enhances the linearity of CMOS PA over a wide range of operation level. The experimental results show that the CMOS PA with proposed scheme has an overall efficiency of 34.6% and a gain of 25.8 dB at an average output power of 27 dBm. Under this condition, the adjacent channel leakage ratio is <–34.8 and 5.4 dBc lower when compared with the use of no linearization technique.

Transient Evolutional Dynamics of Quantum-Dot Molecular Phase Coherence for Sensitive Optical Switching

Atomic phase coherence (quantum interference) in a multilevel atomic gas exhibits a number of interesting phenomena. Such an atomic quantum coherence effect can be generalized to a quantum-dot molecular dielectric. Two quantum dots form a quantum-dot molecule, which can be described by a three-level Λ-configuration model \(\{ |0\rangle ,|1\rangle ,|2\rangle \} \), i.e., the ground state of the molecule is the lower level |0〉 and the highly degenerate electronic states in the two quantum dots are the two upper levels \(|1\rangle ,|2\rangle \). The electromagnetic characteristics due to the |0〉–|1〉 transition can be controllably manipulated by a tunable gate voltage (control field) that drives the |2〉–|1〉 transition. When the gate voltage is switched on, the quantum-dot molecular state can evolve from one steady state (i.e., |0〉–|1〉 two-level dressed state) to another steady state (i.e., three-level coherent-population-trapping state). In this process, the electromagnetic characteristics of a quantum-dot mo...

Topological line defects in graphene for applications in gas sensing

Topological line defects in graphene synthesized in a highly controlled manner open up new research directions for nanodevice applications. Here, we investigate two types of extended line defects in graphene, namely octagonal/pentagonal and heptagonal/pentagonal reconstructions. A combination of density functional theory and non-equilibrium Green's function methods was utilized in order to explore the application potential of this system as an electronic gas sensor. Our findings show that the electric current is confined to the line defect through gate voltage control, which combined with the enhanced chemical reactivity at the grain boundary, makes this system a highly promising candidate for gas sensor applications. As a proof of principle, we evaluated the sensitivity of a prototypical device toward NO2 molecule, demonstrating that it is indeed possible to reliably detect the target molecule.

Indium–gallium–zinc–oxide thin-film transistor with a planar split dual-gate structure

An amorphous indium–gallium–zinc–oxide (a-IGZO) thin-film transistor (TFT) with a planar split dual gate (PSDG) structure has been proposed, fabricated and characterized. Experimental results indicate that the two independent gates can provide dynamical control of device characteristics such as threshold voltage, sub-threshold swing, off-state current and saturation current. The transconductance extracted from the output characteristics of the device increases from [Formula: see text] to [Formula: see text] for a change of control gate voltage from −2 V to 2 V, and thus the device could be used in a variable-gain amplifier. A significant advantage of the PSDG structure is its flexibility in controlling the device performance according to the need of practical applications.