Continuous-time Delta-sigma Modulator Research Articles

A Direct Current-Sensing VCO-Based 2nd-Order Continuous-Time Sigma-Delta Modulator for Biosensor Readout Applications.

A second-order voltage-controlled oscillator (VCO)-based continuous-time sigma-delta modulator (CTSDM) for current-sensing readout applications is proposed. Current signals from the sensor can directly be quantized by the proposed VCO-based CTSDM, which does not require any extra trans-impedance amplifiers. With the proportional-integral (PI) structure and a VCO phase integrator, the capability of second-order noise shaping is available to reduce the in-band quantization noise. The PI structure can be simply realized by a resistor in series with the integrating capacitor, which can reduce the architecture complexity and maintain the stability of the system. The current-steering digital-to-analog converter with tail and sink current sources is used on the feedback path for the subtraction of the current-type input signal. All the components of the circuit are scaling friendly and applicable to current-sensing readout applications in the Internet of Things (IoT). The proposed VCO-based CTSDM implemented in a 0.18-μm standard CMOS process has a measured signal-to-noise and distortion ratio (SNDR) of 74.6 dB at 10 kHz bandwidth and consumes 44.8 μw only under a supply voltage of 1.2 V, which can achieve a Figure-of-Merit (FoM) of 160.76 dB.

A Single Op-Amp Resonator-Based Continuous-Time Sigma–Delta Modulator With Time-Division Switching for Excess Loop Delay Compensation

A Single Op-Amp Resonator-Based Continuous-Time Sigma–Delta Modulator With Time-Division Switching for Excess Loop Delay Compensation

A digital prediction compensation for DR improvement in CT DSM with digital noise coupling

AbstractThis paper presents a prediction‐based dynamic range (DR) compensation technique in continuous‐time (CT) delta ‐sigma modulator (DSM) with digital‐domain noise coupling (DNC) structure. A digital prediction technique is proposed to address the issue of maximum stable amplitude (MSA) loss caused by DNC. The proposed prediction method has been shown to significantly extend the MSA of CT DSM with DNC. Moreover, through the extension of MSA, the DR and SNDR is significantly improved. A CTDSM with proposed compensation achieves a SNDR of 85.1dB at ‐1dBFS and a DR of 89dB.

A Review on Higher Order Continuous-Time Sigma-Delta Modulators for ADC Design

Abstract—In this paper, the concept of adaptive filtering has been proposed. It has been shown that signals often undergo variation in the noise environment encountered. Hence it becomes mandatory to design filters based on noise shaping and adaptive noise cancellation. Such filters are called adaptive filters and are used for applications requiring real time noise cancellation such as speech processing, live video broadcasting etc. The paper presents the structure of Sigma Delta or MASH ADCs which employ recursive encoding. SDM ADCs are also used to convert high bit-count, low- frequency digital signals into lower bit-count, higher-frequency digital signals as part of the process to convert digital signals into analog as part of a digital-to-analog converter (DAC). The paper focuses on the various approaches used thus far for the purpose, citing the pros and cons of each approach. Keywords— Adaptive Filter Design, Noise Filtering, Sigma Delta Modulator (SDM), MASH, Signal to Noise Ratio.

A Second-Order Feedforward VCO-Based ADC with Continuous-Time Sigma-Delta Modulator for EEG Signal Recording Front Ends

A Second-Order Feedforward VCO-Based ADC with Continuous-Time Sigma-Delta Modulator for EEG Signal Recording Front Ends

Automatic Tuning of Negative-R Circuit for High-Performance 95-dB DR 5-kHz Bandwidth Continuous-Time Delta-Sigma Modulator

Automatic Tuning of Negative-R Circuit for High-Performance 95-dB DR 5-kHz Bandwidth Continuous-Time Delta-Sigma Modulator

A 13-Level SC DAC Achieving High Linearity With a Simple DEM for Wideband CT DSMs

Wideband continuous-time (CT) Delta-Sigma modulators (DSMs) generally demand multi-level digital-to-analog converters (DACs), which require a linearization technique to overcome the problem of component mismatches. Dynamic element matching (DEM) is a popular DAC linearization approach but can be challenging to implement in a wideband DSM, particularly when there are many DAC elements. In this manuscript, we introduce a 13-level switched-capacitor (SC) DAC achieving high linearity with a simple DEM that rotates three unit elements only and does not incur excess loop delay. In a traditional CT DSM, a DAC of the SC type increases the amplifier settling requirements and damages the alias rejection. Earlier works have shown that these problems can be solved if the CT DSM adopts a passive RC frontend. A 10-MHz bandwidth CT DSM is designed in the 65-nm CMOS technology to validate the proposed DAC. Simulations show that the DAC enables a spurious-free dynamic range greater than 87.7 dB and a signal-to-noise pulse distortion ratio greater than 80.5 dB under a 1% capacitor mismatch, a 2% reference voltage error, and process variations.

A 24-kHz BW 90.5-dB SNDR 96-dB DR continuous-time delta-sigma modulator using FIR DAC feedback

This paper presents a single bit continuous time delta-sigma modulator (CTDSM) with finite impulse response (FIR) feedback DAC designed for audio applications. By using FIR feedback in the input stage, the linearity requirements of the first integrator are relaxed, and the clock jitter sensitivity is reduced, as seen in a multi-bit quantizers. The choppers, working in conjunction with the FIR DAC, effectively suppresses in-band aliasing noise generated by the chopper in the first integrator. A fast comparator serves as a single-bit quantizer, and the 9.2% TS loop delay eliminates the need for excess loop delay compensation in the modulator. Energy efficient integrators are implemented using the current-starved OTA. The CTDSM prototype was fabricated using a 180-nm CMOS process, achieving a 90.5 dB SNDR and 96 dB DR with a 24 kHz signal bandwidth. The power consumption is 210 μ W, corresponding to a Schreier figure-of-merit value of 171.1 dB.

A New Design of NCFF Compensated Operational Amplifier for Continuous-Time Delta Sigma Modulator

A power-efficient second-order no-capacitor feedforward (NCFF) op-amp has been designed in 180[Formula: see text]nm CMOS process. To attain high gain and better common mode rejection, cross-coupled loading network has been used in each differential stage. The designed op-amp achieves over 40[Formula: see text]dB gain up to 400[Formula: see text]MHz and over 10[Formula: see text]dB open loop gain up to 4[Formula: see text]GHz with 0.87[Formula: see text]mW power consumption. It is suitable for application in continuous-time delta-sigma modulator (CT [Formula: see text]M) with sampling frequency in GHz range.

Behavioral and Electrical Modeling of a 0.5-V Third-Order Continuous-Time Sigma-Delta Modulator with FIR DAC for Audio Applications

Most mobile and wearable devices present digital audio signal processing capabilities. Since the nature of audio signals is analog, there is a need to use analog-to-digital converters (ADCs) with high-resolution for a high signal-to-noise ratio audio acquisition. This paper presents the high-level modeling and design of a continuous-time third-order sigma-delta modulator (CT-SDM) with an FIR DAC for audio devices, using a supply voltage of 0.5 V. The design is divided in three steps and is carried out using the Delta-sigma toolbox and a discrete-time to continuous-time (DT-CT) transformation. First, the schematic implementation with verilogA models is done to estimate the first-integrator amplifier specifications for the modulator to provide 14 bits of ENOB. Following, a two-stage inverter-based amplifier is designed and used to verify the design strategy. Finally, a transistor-level implementation of OTAs and comparator is done to evaluate the CT-SDM performance. An in-depth analysis and discussion are presented to explain the achieved results with those transistor-level circuits.

An Intrinsically Linear 13-Level Capacitive DAC for Delta Sigma Modulators

Mismatch of the digital-to-analog converter (DAC) elements is the major limitation for Signal to Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) in multi-bit Delta Sigma Modulators (DSM). In this article we extend a previously introduced technique to build an intrinsically linear 13 level DAC. An exemplary Switched-Capacitor (SC) 13-levels 20 kHz discrete-time DSM employing this technique is simulated and achieves an SFDR higher than 100 dBc on circuit level in presence of considerable capacitor mismatch. The presented DAC architecture is not limited to be used in a discrete-time modulator, but could also be employed in a Continuous-Time DSM (CTDSM).

An 81.6 dB SNDR 15.625 MHz BW Third-Order CT SDM With a True Time-Interleaving Noise-Shaping Quantizer

This work introduces a time-interleaved architecture to tackle the speed-resolution bottleneck of the noise-shaping (NS) successive approximation register (SAR) quantizer in a continuous-time (CT) sigma-delta modulator (SDM). A critical insight is that introducing a delay in the NS quantizer feedback loop enables complete parallelization of the NS quantizer operations. The extra time from parallelization greatly relaxes loop filtering and residue integration and enables a high quantizer resolution. Furthermore, the extra time in the feedback loop allows data weighted averaging (DWA), which eliminates the need for calibration. The prototype comprises a second-order CT front-end and a fully interleaved first-order NS quantizer. The prototype is fabricated in a 28 nm process, occupies 0.072 mm2 and consumes 6.4 mW. The peak signal-to-noise ratio (SNR), signal-to-noise-distortion ratio (SNDR), and dynamic range (DR) are 83.9, 81.6, and 84.8 dB, respectively, in a 15.625 MHz bandwidth. The corresponding Schreier SNDR figure of merit (FoM) is 175.5 dB.

Complete design approach of a 3rd order continuous-time sigma-delta ADC with FIR feedback and low-noise low-distortion op-amp achieving 101.8 dB SNDR and −110dB THD

This paper presents a step-by-step design approach of a 3rd order continuous-time sigma-delta modulator with a 4-tap FIR feedback DAC achieving 107 dB DR (A-weighted), −110 dB THD and an SNDR of 101.8 dB. The THD is achieved through a fully differential feed-forward compensated op-amp that maintains high linearity with the aid of a class AB output stage and an optimum bias current through a CMFB loop. The modulator consumes 322.5uW of power while taking an area of 0.2925 mm2.

Design and Implementation of a Second Order Continuous-Time ΣΔ Modulator for ECG Signal Acquisition

The recent developments in biosignal acquisition devices for continuous supervision of cardiovascular signs of high-risk patients require a high-precision and low-power Analog Front End (AFE) circuit. The proposed design adopts Continuous-Time (CT) Sigma-Delta Modulator (ΣΔM) architecture to achieve high resolution and SIgnal-to-Noise And Distortion ratio (SINAD) requirements. The proposed modulator is a second-order CT-ΣΔM with Cascade of Integrators Feed-Forward (CIFF) architecture that consists of a CT loop filter, a single-bit quantizer, and a Digital-to-Analog Converter (DAC). The use of single-bit quantization in the design reduces circuit complexity and power consumption. To use the designed ΣΔM for measuring ECG signals, a bandwidth (Bw) of 150 Hz is considered with a sampling frequency (fs) of 153.6kHz to achieve an oversampling ratio of 512. The design is simulated in a standard Cadence Virtuoso EDA tool at 180nm CMOS technology, operating at 1.8V supply voltage at the block level. The simulation results for the designed modulator show that SINAD is 104.5dB, the Effective Number Of Bits (ENOB) is 17.06bits, with power consumption of 24µW, and achieves Schreier’s Figure-Of-Merit (FOM) equal to 172.45dB.

A New Low-Noise I-Squared Buck Converter Suitable for Wireless Sensor Networks With Dual-Current-Acceleration Techniques

This paper proposed a new low-noise I-squard 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> -order continuous-time-delta-sigma-modulation (CT-DSM) buck converter suitable for wireless sensor networks with dual-current-acceleration (DCA) techniques. First, it adopts the second-order CT-DSM scheme, which can effectively utilize the oversampling and the noise shaping techniques to disperse the noise and push it to higher frequencies. Second, the use of the pseudo-inductor-current-sensor can increase the bandwidth of the closed-loop gain and consequently speeds up the transient response of the converter. Third, the dynamic-current regulator utilizes the principle of current charging and discharging to make the converter respond faster when the load changes dynamically. Fourth, this paper combines the pseudo-inductor-current-sensor and the dynamic-current regulator to realize the dual-current-acceleration technique, which can accelerate the transient response by up to 45.5%. The proposed converter is designed and fabricated in TSMC 0.18μm 1P6M CMOS process, and the chip area is 1.065 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . When the load current changes from 50mA to 500mA and 500mA to 50mA, the transient responses are 2.4μs and 3μs, respectively, and the peak efficiency is 92.4%. The measurement result of ONR is 78.087dB, with the sampling frequency of 10 MHz.

A 40 MHz 11-Bit ENOB Delta Sigma ADC for Communication and Acquisition Systems.

This paper describes a Delta Sigma ADC IC that embeds a 5th-order Continuous-Time Delta Sigma modulator with 40 MHz signal bandwidth, a low ripple 20 to 80 MS/s variable-rate digital decimation filter, a bandgap voltage reference, and high-speed CML buffers on a single die. The ADC also integrates on-chip calibrations for RC time-constant variation and quantizer offset. The chip was fabricated in a 1P7M 65 nm CMOS process. Clocked at 640 MHz, the Continuous-Time Delta Sigma modulator achieves 11-bit ENOB and 76.5 dBc THD up to 40 MHz of signal bandwidth while consuming 82.3 mW.

A 10-MHz 85.1-dB SFDR 1.1-mW continuous-time Delta–sigma modulator employing calibration-free SC DAC and passive front-end low-pass filter

This article demonstrates the circuit technique of a highly power-efficient continuous-time (CT) Delta–sigma modulator (DSM) based on a switched-capacitor (SC) feedback digital-to-analog converter (DAC) and a passive front-end low-pass filter (LPF). The technique addresses the clock sensitivity issue of conventional DACs while maintaining the alias rejection. It is validated by a fourth-order CT DSM prototype fabricated in 65-nm CMOS technology. The input stage of the DSM is an active-RC integrator merged with a passive front-end LPF. A resonator follows and realizes the cascade of resonators with feedforward (CRFF) structure. The accurate feedback loop employs a highly linear and calibration-free 5-level SC DAC. Based on the linear periodically time-varying (LPTV) system model, an exact analysis is given to explain the effects of the passive LPF and SC DAC combo on the signal transfer function (STF), and hence, on the alias rejection. The prototype DSM achieves a 70.2-dB signal to noise and distortion ratio (SNDR) and an 85.1-dB spurious-free dynamic range (SFDR) in a 10-MHz bandwidth, while dissipating 1.1 mW with a 1-V supply. The modulator achieves a 65.4-dB alias rejection and confirms the closed-form analytical results.

An 18.1 mW 50 MHz-BW 76.4 dB-SNDR CTSDM With PVT-Robust VCO Quantizer and Latency-Free Background-Calibrated DAC

This paper presents a continuous-time sigma-delta modulator (CTSDM) with a voltage-controlled-oscillator-based (VCO-based) integrating quantizer. A background replica-based calibration technique is proposed to alleviate the impact of the process, voltage supply, and temperature (PVT) variations on the tuning characteristic and current consumption of the VCO-based quantizer. Matching between the replica VCO and the main VCO in the proposed calibration is not needed. A latency-free background calibration technique is also proposed to eliminate the distortions caused by the DAC mismatch. The prototype VCO-based CTSDM is fabricated in a 40 nm CMOS and achieves SNDR/SFDR/DR of 76.4 dB/91.7 dBc/79.6 dB, respectively, within a 50 MHz bandwidth (BW) at 1.6 GHz sampling frequency. The measured SNDR varies within ±1 dB over a temperature range of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0\sim 80~^{\circ }\text{C}$ </tex-math></inline-formula> and a voltage supply variation of ±10%, across different tested samples. The power consumption is 18.1 mW, achieving a Schreier Figure of Merit (FoMS) of 170.8 dB.

A 2.16-μW Low-Power Continuous-Time Delta–Sigma Modulator With Improved-Linearity Gₘ for Wearable ECG Application

This brief presents a 2.16 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> low-power third-order single-bit continuous-time delta-sigma modulator (CTDSM) for electrocardiogram (ECG) signal acquisition application. The proposed CTDSM uses an active-RC (A-RC) integrator as a first integrator and an improved linearized <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{m}$ </tex-math></inline-formula> -C integrator for the second and third integrators, respectively. The mixed-integrator structure helps to mitigate the trade-offs between power consumption and resolution. Moreover, a source-degenerated auxiliary differential pair circuit is used for the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{m}$ </tex-math></inline-formula> -C integrators to improve their linearity. By using A-RC and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{m}$ </tex-math></inline-formula> -C integrators together along with an improved-linearized <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{m}$ </tex-math></inline-formula> block, the total power consumption was measured as 2.16 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> with a peak signal-to-noise ratio of 80.1 dB, signal-to-noise, and distortion ratio of 78.4 dB, and a dynamic range of 81.4 dB with a bandwidth of 250 Hz. Furthermore, a real-time ECG signal was successfully captured in an ECG acquisition system that consisted a heart-rate sensor and a signal acquisition circuit, including the proposed CTDSM.

Design of High-Resolution Continuous-Time Delta–Sigma Data Converters With Dual Return-to-Open DACs

We present design techniques for single-bit continuous-time delta–sigma modulators that attain high resolution (>16 bits) over a bandwidth (BW) that is more than ten times the audio range. We introduce the zapped, virtual-ground-switched dual return-to-open DAC which is immune to ISI and other transition-dependent errors. FIR feedback facilitates chopping, improves clock-jitter sensitivity and the loop filter’s linearity. We show that the compensation FIR DAC, which is typically bulky, can be implemented in an extremely power- and area-efficient manner in a single-bit modulator using a capacitive DAC and passive summation. Thanks to these techniques, the fabricated prototype achieves 103.2-/104.3-dB signal to noise and distortion ratio (SNDR)/signal to noise ratio (SNR) in a 250-kHz bandwidth while operating at 48 MS/s. Consuming 17.7 mW from a 1.8-V supply, the modulator occupies 1.1 mm 2 in a 180-nm CMOS process. The Schreier (SNDR) figure of merit (FoM) is 174.7 dB.