Continuous-time Low-pass Filter Research Articles

A PVT-Robust and 73.9 mHz High-Pass Corner Instrumentation Amplifier with an SCF-SCR-PR Hybrid Feedback Resistor

Analog front-end (AFE) circuits play an important role in the acquisition of physiological signals with low-level amplitudes (from tens of μV to tens of mV) and broadband low-frequency ranges (from sub-Hz to several hundred Hz). Possessing a high input impedance, an instrumentation amplifier (IA) accurately amplifies signals with low amplitude and low frequency, making it suitable for AFE circuits. This work demonstrates a capacitively coupled IA whose feedback resistance is realized by the proposed hybrid resistor, consisting of a switched-capacitor low-pass filter, a switched-capacitor resistor, and a continuous-time low-pass filter. The capacitively coupled IA achieves tera-ohm (TΩ) resistance and is insensitive to process, voltage, and temperature (PVT) variations. The simulation results show that the proposed IA illustrates a high-pass corner of 73.9 mHz, and the change of its high-pass corner with temperature is 0.05 mHz/°C. With the variation in the PVT corners, the difference between the maximum and minimum values of the high-pass corner of the proposed capacitively coupled IA is only 0.06 Hz. The design was implemented in a 130 nm standard CMOS process. The AFE with the proposed capacitively coupled IA achieves a 53.9 dB signal-to-noise and distortion ratio (SNDR) and 69.5 dB total harmonic distortion (THD).

A 0.5-V 3.69-nW Complementary Source-Follower-C Based Low-Pass Filter for Wearable Biomedical Applications

Ultra-low-power circuits that can work under a low-voltage supply are in great demand in future wearable biomedical applications, which tend to be integrated with low-output-voltage energy harvesting devices. In this paper, we present a low-voltage low-power continuous-time low-pass filter (CT-LPF), which is indispensable in biomedical systems. When a low-voltage supply is used, it is necessary to make the output quiescent voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</sub> ) stable in the LPF, otherwise the dynamic range will be reduced. Conventional Source-follower (SF) based topologies can achieve ultra-low-power consumption. However, the difference of the input and output V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</sub> is sensitive to process and temperature variations. In this work, a complementary SF based topology with a bulk-common-mode-feedback (B-CMFB) circuit is proposed to keep the output V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</sub> tracking the input VQ and immune to the process and temperature variations. A 4 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> -order LPF using the proposed topology has been implemented in a standard 0.18 μm CMOS process, which achieves a power consumption of only 3.69-nW under a 0.5-V voltage supply with a bandwidth of 200 Hz. Measurement results show that the input-referred noise is 91.9 μV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> . The IIP3 is 5.0 dBm and the dynamic range (DR) is 48.5 dB. The active chip area is only 0.074 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The proposed LPF achieves both ultra-low power consumption with a 0.5-V supply and a stable output V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</sub> immune to process and temperature variations, which is suitable for low-supply-voltage biomedical systems.

An On-Chip Built-in Linearity Estimation Methodology and Hardware Implementation

An on-chip built-in linearity estimation methodology for a hybrid baseband chain is proposed. The proposed hybrid baseband chain consists of a continuous-time low-pass filter and a discrete-time (DT) finite impulse response filter with a compacted two-stage 3-tap harmonic cancellation (HC). This HC-32 architecture achieves notching at specific programmable frequency points. To estimate the filter linearity, two-tone test signals are injected, and the spectrum power of the DT filter’s output is measured by a power detector. By changing the sampling frequency, the DT filter can switch between the normal operation mode, which allows the two test tones to pass through, or the tone suppression mode, which notches the two test tones and exposes the IM3 tone power. The proposed on-chip linearity estimation methodology is experimentally verified. A comparison between the power measured in the proposed two modes reveals how well is the filter linearity. The proposed baseband chain is fabricated in 130-nm standard CMOS technology, occupying a 0.146-mm2 silicon area. Measurement results shows a suppression of 55 dB on the test tone power.

Analog Statistical Design for Manufacturability Using Linear and Nonlinear Response

Manufacturing yield, overkill, and defect level can limit the feasibility of analog circuits in SoCs. The conventional method of handling process and environmental variation is to assign the design margin such that the design meets specifications at several processes and environmental corners. However, checking only a few extreme corners limits performance more than the more rigorous statistical approach of computing manufacturing and quality figure of merit. On the other hand, the statistical approach requires transistor level simulation of hundreds or thousands of samples, not just a few corners, and hence is very time-consuming. This paper gives a way to sidestep the problem by characterizing each of many samples of building blocks once at the transistor level. The building blocks are scalable so that statistics are preserved when a building block is adjusted to the requirement of a higher level design. Many design scenarios may be rapidly explored by assembling and scaling the building block samples without SPICE simulation. A continuous-time low-pass filter design example is used to extract the requirements of the building block approach. The requirements include a method to assemble building blocks (biquad element for the example) into a filter design while preserving the statistics that would have been extracted by simulation of the entire filter at the transistor level. The assembly method for both linear and nonlinear response is proposed.

Fully‐differential flipped‐source‐follower low‐pass analogue filter in CMOS 28 nm bulk

This study presents a novel low-pass continuous-time filter based on the voltage flipped-source-follower (SF). The filter efficiently operates in CMOS 28 nm and improves the SF filters state-of-the-art thanks to a dedicated circuit that operates in fully-differential fashion (instead of the pseudo-differential typically used in state-of-the-art SF filters) with a dedicated Common-Mode-Feedback circuit. Thus this work extends the application of the SF filtering stages to the nm-range technologies where threshold voltage (VTH) is only two times lower than the supply voltage (VDD) for what regards standard-process MOS transistors. In order to validate the design concept, the proposed filter has been designed in CMOS 28 nm technology. Extensive simulation results of a 131 MHz −3 dB frequency proof-of-concept second-order filter are proposed. The device consumes 510 µW power from a single 1 V supply-voltage. In-band integrated noise is 160 µVRMS and IIP3 is 19 dBm for 20 and 21 MHz input tones frequencies. Simulation results lead to 166 J−1 figure-of-merit, outperforming the analogue filter state-of-the-art.

21.5 dBm‐IIP3 22.5 MHz fourth‐order follow‐the‐leader‐feedback analogue filter

A 4th-order single-loop follow-the-leader-feedback (FLFB) low-pass continuous-time filter in CMOS 0.18 µm is hereby presented. The outstanding FLFB noise behaviour is exploited to allocate the power consumption to linearity performance. The low-pass filter prototype features 22.5 MHz−3 dB frequency, 21.5 dBm-IIP3 and 76 µVRMS input referred in-band integrated noise. The overall power consumption is 7 mA from a 1.8 V supply voltage. The signal-to-noise ratio for a −40 dB-total harmonic distortion is 69 dB.

A 0.7-MHz–10-MHz ${\rm CT}+{\rm DT}$ Hybrid Baseband Chain With Improved Passband Flatness for LTE Application

A hybrid baseband chain for Long-Term Evolution (LTE) was implemented in a TSMC 65-nm CMOS process. It has an active area of 0.75 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a power consumption of 10.8 mW at a supply of 1.8 V. The proposed baseband chain consists of a continuous-time (CT) lowpass filter and a charge-domain discrete-time (DT) filter with a variable gain amplifier (VGA) and a DC-offset canceller (DCOC). The passband distortion of the DT filter is calibrated by varying the quality (Q)-factor of the CT filter, which is easily tuned by switched-resistors. The charge-domain DT filter is adopted for anti-aliasing filtering and efficient interferer rejection with small size and low power consumption. By combining the CT and the DT filters, the baseband chain acquires improved passband flatness with an in-band ripple of less than 1 dB from 0.7 MHz to 10 MHz. It also has a gain of 50.8 dB, input-referred noise of 22.8 nV/√Hz, and an out-of-band IIP3 of 29 dBm.

Design of Low Voltage Low Power LPF for WSN Node

A fourth-order low-pass continuous-time filter for a WSN transmitter is presented. The active RC filter was chosen for the high linearity, designed by using the leapfrog topology imitates the passive filter. The operation amplifier (op-amp) adopted by the filter is feed-forward operation amplifier, which could get the GBW as large as possible under the low power consumption. The cut-off frequency deviation due to the process corner, aging and temperature deviation is adjusted by an automatic frequency tuning circuit. The filter in a 0.18μm RF CMOS technology consumes 1mW from a 1V power supply. The measured results of the chip show that the bandwidth is about 1.5MHz. The voltage gain of filter is about-4.5dB with the buffer, the ripple in the pass-band is lower than 0.5 dB, and the channel rejection ratio is larger than 30dB at 4MHz.

A Reconfigurable Direct RF Receiver With Jitter Analysis and Applications

In typical direct radio frequency (RF) sampling receivers, the sample clock jitter results in SNR degradation on received signals that increases log linearly with RF signal frequency. De-jittering received signals is computationally expensive, especially for wideband communications signals, because the induced jitter on received signals varies as a function of RF signal frequency. This paper considers a reconfigurable direct RF receiver (RDRFR) that has a stair-step jitter pattern as a function of RF signal frequency. The RDRFR uses a two-stage sampling circuit. In the first stage, the RF input is bandpass filtered and pulse sampled without quantizing the signal. The discrete-time analog signal is then interpolated with a continuous time low-pass filter, then sampled and quantized by a traditional analog-to-digital converter. With this two-stage sampling circuit, the induced signal jitter from the RF sampling is identical for all in-band signals and is the same to within an integer scale factor for all signals, in-band or out-of-band. This key circuit property means that it is possible to remove jitter with very low computational complexity in the RDRFR. Furthermore, this result can be exploited to improve system performance with non-ideal anti-alias filters by identifying non-desired signals caused by out-of-band leakage.

A High-Linearity 264-MHz Source-Follower-Based Low-Pass Filter with High-Q Second-Order Cell for MB-OFDM UWB

Source-follower-based (SFB) continuous-time low-pass filters (LPF) have the advantages of low power and high linearity over other filter topologies. The second-order SFB filter cells, which are key building blocks for high-order SFB filters, are often realized by composite source follower with positive feedback. For a single branch 2nd-order SFB cell, the linearity drops severely at high frequencies in the pass band because its slew-rate is restricted by the Q factor and the pole frequency. The folded 2nd-order SFB cell provides higher linearity because it has two DC branches, and hence has another freedom to increase the slew rate. However, because of the positive feedback, the folded and unfolded 2nd-order SFB cells, especially those with high Q factors, tend to be unstable and act as relaxation oscillators under given circuit parameters. In order to obtain higher Q factor, a new topology for the 2nd-order SFB cell without positive feedback is proposed in this paper, which is unconditionally stable and can provide high linearity. Based on the folded 2nd-order SFB cell and the proposed high-Q SFB cell, a 264MHz sixth-order LPF with 3 stages for ultra wideband (UWB) applications is designed in 0.18µm CMOS technology. Simulation results show that the LPF achieves an IIP3 of above 12.5dBm in the whole pass band. The LPF consumes only 4.1mA from a 1.8V power supply, and has a layout area of 200µm × 150µm.

A 0.55 V 60 dB-DR Fourth-Order Analog Baseband Filter

A 0.55 V supply voltage fourth-order low-pass continuous-time filter is presented. The low-voltage operating point is achieved by an improved bias circuit that uses different opamp input and output common-mode voltages. The fourth-order filter architecture is composed by two active- Gm-RC biquadratic cells, which use a single opamp per-cell with a unity-gain-bandwidth comparable to the filter cut-off frequency. The - 3 dB filter frequency is 12 MHz and this is higher than any other low-voltage continuous-time filter cut-off frequency. The -3 dB frequency can be adjusted by means of a digitally-controlled capacitance array. In a standard 0.13 mum CMOS technology with VTHN ap 0.25 V and VTHP ap 0.3 V, the filter operates with a supply voltage as low as 0.55 V. The filter (total area=0.47 mm2) consumes 3.4 mW. A 8 dBm-in-band IIP3 and a 13.3 dBm-out-of-band IIP3 demonstrate the validity of the proposal.

A 240-MHz Low-Pass Filter With Variable Gain in 65-nm CMOS for a UWB Radio Receiver

An integrated fifth-order continuous-time low-pass filter for a WiMedia ultrawideband radio receiver is described in this paper. The prototype filter is realized with a passive pole at the filter input and a fourth-order leapfrog filter in which the gm-C technique with pseudodifferential transconductors is used. The transconductors do not include internal nodes, and they are designed to have a nominal 26-dB dc gain, of which process, voltage, and temperature variations are controlled by means of a negative resistance circuit. The losses of the low-dc-gain filter integrators are already taken into account in the filter synthesis. The passband edge frequency of the implemented filter is 240 MHz in order to receive multiband-orthogonal-frequency-division-multiplexing signals using the direct-conversion topology. The voltage gain of the filter can be controlled from 9 to 43 dB in the 1-dB gain steps. The filter achieves a 7.8-nVradicHz input-referred noise density, a -8-dBV out-of-band third-order intermodulation intercept point, and a +15-dBV out-of-band second-order intermodulation intercept point. The circuit uses a 1.2-V supply and has been fabricated in a modern 65-nm CMOS technology.

A 5.2 mW 240–550 MHz continuous-time low-pass filter and VGA for a UWB receiver in 0.18 μm CMOS process

A very low-power wide-band CMOS continuous-time low-pass filter for a ultra wideband system receiver in 0.18-μm CMOS technology is proposed. The cutoff frequency of the fourth-order LPF can be tuned within 240---550 MHz. The gain of the filter is tuned about 44 dB which can omit the variable gain amplifier (VGA) block. An IIP3 of 17.4 dBm is achieved for a power consumption of 5.2 mW from a 1.8 V power supply. Merging LPF and VGA into one block can efficiently reduce the power consumption and the chip area of the analog baseband channel while achieving a high linearity.

Low-Power Architecture and Circuit Techniques for High-Boost Wide-Band &lt;formula&gt; &lt;tex&gt;$G_m$&lt;/tex&gt;&lt;/formula&gt;&amp;ndash;&lt;formula&gt;&lt;tex&gt;$C$&lt;/tex&gt;&lt;/formula&gt; Filters

A 330-MHz fifth-order G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -C continuous-time low-pass filter with 24-dB boost is presented. Existing solutions are found to be unsuitable for low-power, wide-band, and high-boost operation. The proposed solution realizes two symmetric real axis zeros by efficiently combining transfer functions associated with all nodes of cascaded biquad cells. Application of Gilbert cell as a variable transconductor, for achieving constant parasitic capacitance across wide programmability range, is illustrated. A new common-mode feedback error amplifier that improves common-mode accuracy without compromising on bandwidth or circuit complexity is introduced. A prototype is fabricated in a standard 0.35-mum CMOS process. Experimental results show -41 dB of IM3 for 250-mV peak-peak swing with 43 mW of power dissipation

A 4th-Order Active-&lt;tex&gt;$G_m$&lt;/tex&gt;-RC Reconfigurable (UMTS/WLAN) Filter

A fourth-order low-pass continuous-time filter for a UMTS/WLAN receiver of a reconfigurable terminal is presented. The filter uses the cascade of two Active-Gm-RC biquad cells. A single opamp is used for each biquad and its unity-gain-bandwidth is comparable to the filter cut-off frequency. Thus, the opamp power consumption is strongly reduced w.r.t. other closed-loop filter configurations. The cut-off frequency deviation due to the technological spread, aging and temperature variation is adjusted by an on-chip tuning circuit. The device in a 0.13 mum CMOS technology occupies a 0.9 mm2 area and it consumes 3.4 mW and 11 4.2 mW for the UMTS and WLAN, respectively. The full chip has been designed using an automatic design tool, which is validated by the agreement between the experimental results and the expected performance

A CMOS 140-mW fourth-order continuous-time low-pass filter stabilized with a class AB common-mode feedback operating at 550 MHz

A 550-MHz linear-phase low-pass continuous-time filter is described. The operational transconductance amplifier (OTA) is based on complementary differential pairs in order to achieve high-frequency operation. A common-mode feedback (CMFB) based on a Class AB amplifier with improved stability at high frequencies is introduced. Results for the stand alone OTA show a unity gain frequency of 1 GHz while the excess phase is less than 5/spl deg/. The filter is based on G/sub m/-C biquads and achieves IM3 <-40 dB for a two-tone input signal of -10 dBm each. The power consumption of the fourth-order filter is 140 mW from supply voltages of /spl plusmn/1.65 V. The chip was fabricated in a standard 0.35-/spl mu/m CMOS technology.

A Low-Power Reconfigurable Analog Filter for UMTS/WLAN Receivers

A highly integrated low-power analog filter in 0.13μm CMOS able to be reconfigured in order to be used in UMTS and WLA N applications is reported. The order low-pass continuous-time filter is embedded in the receiver path. The filter is made up by the cascade of 2 Active Gm-RC low-pass biquadratic cells. The use of Active Gm-RC cells guarantees law power performance since they use low fu opamps. Thus, it presents low cost and low power characteristics. In fact, a little area overhead is required since the filter can share capacitors as well as opamps in both operations modes.

A near-infrared heart rate measurement IC with very low cutoff frequency using current steering technique

A near-infrared heart-rate measurement IC that processes the photoplethysmographic signal was designed using a 0.35-/spl mu/m CMOS technology. The IC consists of a current-to-voltage (I-V) converter, a buffer, a sample-and-hold circuit, a second-order continuous-time low-pass filter (CT-LPF), a comparator, and a timing circuit that is used to pulse the external light-emitting diode with a very low duty cycle to reduce its power consumption. The current steering technique is employed in the design of the CT-LPF to meet the requirement for very low cutoff frequency. The circuit operates from a 3-V lithium battery, occupies a core area of 0.46 mm/sup 2/ and has a power consumption of 4.5 mW. The measurement results corroborate with simulation results and show that the CT-LPF can achieve a cutoff frequency of as low as 0.25 Hz. This demonstrates the feasibility of current steering technique in the design of filter for low-frequency application.

Novel single-stage second-order structure for low-pass wide-band low-power continuous-time filters

A novel single-stage second-order structure for Gm-C filters is presented. It allows ample reduction in hardware and thus power consumption. Moreover, due to exploiting otherwise parasitic poles, the structure allows much higher bandwidth than in conventional designs, be achieved. To verify effectiveness of new concept, and based on the new approach to implement second-order stages, a third-order and a fifth-order continuous-time low-pass filters were implemented. The filters fabricated in a 0.5 μ m CMOS process, achieved more than 430 MHz, - 3 dB bandwidth and less than - 55 dB THD for a 400 m V p – p 100 MHz input signal. All these accomplished with a factor of about four reduction in hardware and power. The bandwidth, output voltage swing, and dynamic range are far larger than those of any other CMOS low-pass filters thus far reported, which have bandwidth higher than 100 MHz.

A Mixed-Signal Approach for Tuning Continuous-Time Low-Pass Filters

A mixed-signal approach for tuning the bandwidth of continuous-time low-pass filters is presented. The tuning loop uses common circuit blocks (a data converter and digital filters). Simulation results are presented for a number of filters, and measured results are presented for tuning second-order and fourth-order filters.