An On-Chip Built-in Linearity Estimation Methodology and Hardware Implementation

Abstract

An on-chip built-in linearity estimation methodology for a hybrid baseband chain is proposed. The proposed hybrid baseband chain consists of a continuous-time low-pass filter and a discrete-time (DT) finite impulse response filter with a compacted two-stage 3-tap harmonic cancellation (HC). This HC-32 architecture achieves notching at specific programmable frequency points. To estimate the filter linearity, two-tone test signals are injected, and the spectrum power of the DT filter’s output is measured by a power detector. By changing the sampling frequency, the DT filter can switch between the normal operation mode, which allows the two test tones to pass through, or the tone suppression mode, which notches the two test tones and exposes the IM3 tone power. The proposed on-chip linearity estimation methodology is experimentally verified. A comparison between the power measured in the proposed two modes reveals how well is the filter linearity. The proposed baseband chain is fabricated in 130-nm standard CMOS technology, occupying a 0.146-mm2 silicon area. Measurement results shows a suppression of 55 dB on the test tone power.