Analog Statistical Design for Manufacturability Using Linear and Nonlinear Response

Yu-Shan Wang

doi:10.1109/access.2019.2929049

Abstract

Manufacturing yield, overkill, and defect level can limit the feasibility of analog circuits in SoCs. The conventional method of handling process and environmental variation is to assign the design margin such that the design meets specifications at several processes and environmental corners. However, checking only a few extreme corners limits performance more than the more rigorous statistical approach of computing manufacturing and quality figure of merit. On the other hand, the statistical approach requires transistor level simulation of hundreds or thousands of samples, not just a few corners, and hence is very time-consuming. This paper gives a way to sidestep the problem by characterizing each of many samples of building blocks once at the transistor level. The building blocks are scalable so that statistics are preserved when a building block is adjusted to the requirement of a higher level design. Many design scenarios may be rapidly explored by assembling and scaling the building block samples without SPICE simulation. A continuous-time low-pass filter design example is used to extract the requirements of the building block approach. The requirements include a method to assemble building blocks (biquad element for the example) into a filter design while preserving the statistics that would have been extracted by simulation of the entire filter at the transistor level. The assembly method for both linear and nonlinear response is proposed.

Highlights

Mixed-signal Application Specific IC (ASIC) and Systemon-Chip (SoC) integrate analog components such as PLLs, IOs, filters, analog-to-digital and digital-to-analog converters, thermal sensors, etc. within larger digital systems with component counts and areas considerably less than the digital system
Each design alternative, i.e. different topology, transistor implementation, responds differently to manufacturing variations and may require different testing strategies [1] resulting in different sensitivities to the final SoC product manufacturing and quality Figuresof-Merit (FoM), viz. yield, test-escape, overkill and defect level
It is difficult to include manufacturing and quality figures-of-merit affected by process variation in the

Summary

INTRODUCTION

Mixed-signal Application Specific IC (ASIC) and Systemon-Chip (SoC) integrate analog components such as PLLs, IOs, filters, analog-to-digital and digital-to-analog converters, thermal sensors, etc. within larger digital systems with component counts and areas considerably less than the digital system. The methodology is demonstrated by evaluating two different design alternatives for a continuous-time low pass filter with a pass-band gain of 0dB, bandwidth of 200kHz and stop-band rejection of >30dB at 435kHz in a 45nm CMOS technology to maximize the manufacturing and quality FoMs. Cascaded biquads (Fig. 2) are used to realize the low-pass filter transfer function, HF (s), in (2) since it is a more general topology that can be used to implement a transfer function that is a quotient of two polynomials. BUILDING BLOCK METHODOLOGY FOR MANUFACTURING AND QUALITY FOM PREDICTION As described, a cascaded biquad filter design is used to demonstrate the design methodology for manufacturing Filter use requirement such as DC gain, cut-off frequency, in-band-ripple, stop-band attenuation and linearity are listed in Table-1. The what-if design/test/use scenarios for the filter design examples given in this paper were coded in Python and were executed in real time on a PC

BIQUAD LIBRARY AND CHARACTERIZATION

ESTIMATION OF FILTER FREQUENCY RESPONSE

RESULTS

VIII. CONCLUSION