Context Switching Research Articles

Context change and associative learning

This article reviews the effects of changing the background context on performance in associative learning tasks in humans and animals. The findings are complementary and consistent over animal conditioning (Pavlovian and instrumental learning) and human predictive learning and memory paradigms. In many cases, a context change after learning can have surprisingly little disruptive influence on performance. Extinction, or retroactive interference treatments more generally, is more context-specific than the initial learning. Contexts become important if the participant is exposed to any of several treatments that involve prediction error, which may serve to increase attention to the context. Contexts also become important if they are given predictive or informational value. Studies of instrumental (operant) learning are further consistent with the idea that the context might also influence affordances that support voluntary actions. Context switch effects are not universal, but mainly occur when certain attention and perception processes can come into play. WIREs Cogn Sci 2013, 4:237-244. doi: 10.1002/wcs.1225 This article is categorized under: Psychology > Learning.

The inertia of conditioned craving. Does context modulate the effect of counterconditioning?

Previous research (Van Gucht, Baeyens, Vansteenwegen, Hermans, & Beckers, 2010) showed that a cue, initially paired with chocolate consumption, did not cease to elicit craving for chocolate after extinction, but did so after counterconditioning (CC). CC moreover was more effective than extinction in changing evaluations, in disrupting reported cue-elicited expectancy to get to eat chocolate, and in reducing actual consumption. The present research aimed to investigate whether the advantage of CC over extinction in changing acquired craving and liking would survive a change in context after CC. One group of participants received acquisition, CC and a final test all in the same context A (AAA-COUNTER-group). A second group received CC in a different context B (ABA-COUNTER-group). To compare the degree of any renewal after CC to renewal after extinction, a third group received extinction rather than CC in context B (ABA-EXT-group). Data indicate that a context switch after CC/extinction (ABA-groups) results in a return of cue-elicited approach tendencies and US-expectancies that were reduced or reversed after CC/extinction (renewal). As before, acquired liking is reduced only through CC, not by an extinction procedure. After CC in a different context, a return to the original acquisition context did not renew liking.

Porting RT-Thread to Cortex-M3 Processor

Based on the analysis of the characteristics of the RT-Thread and Cortex-M3, show the superiority of the combination of the two. On the study of RT-Thread and Cortex-M3 system structure and characteristics, RT-Thread is ported to the Cortex-M3 Skillfully. The PendSV exception of Cortex-M3 which can automatic saves part of the registers is used in the process of context switching to reduce the time of thread context switching, and improve the real-time property. This can be as a state-of-the-art design architecture used in intelligent instrument. The system is stable in the practical test, and possessed of popularization and application value.

마이크로컨트롤러 인터럽트를 사용한 임베디드시스템의 다중 상태기계 모델링 기반 구현 기법

This paper presents a technique to implement embedded systems using interrupts of the one-chip microcontroller with many peripherals based on a multiple finite state machines model. The multiple finite state machine model utilizes the structure of FSMD used for hardware design and the features of flow control by interrupts. The main finite state machine corresponds to the main program and the sub-state machines corresponds to the interrupt subroutines. Therefore, interrupts from the peripherals can be processed immediately in the sub-state machines. The request and reply variables are used to interface between the finite state machines. Additional operating system is not necessary for the context switching between the main state machine and the sub-state machine, because the flow-control caused by interrupt can be replaced with the switching. An embedded system modeled on multiple finite state machine with ASM charts can be easily implemented by the conversion of ASM charts into C-language programs. This implementation technique can be easily adopted to the hardware oriented embedded systems because of the detail description of the model and the fast response to the interrupt events in the sub-state machine.

Virtualizing on-chip distributed ScratchPad memories for low power and trusted application execution

Emerging multicore platforms are increasingly deploying distributed scratchpad memories to achieve lower energy and area together with higher predictability; but this requires transparent and efficient software management of these critical resources. In this paper, we introduce the concept of ScratchPad Memory virtualization, a hardware/software run-time layer (called SPMVisor) that virtualizes the scratchpad memory space in order to facilitate the use of distributed SPMs in an efficient, transparent and secure manner. We introduce the notion of virtual scratchpad memories (vSPMs), which can be dynamically created and managed as regular SPMs. The SPMVisor exploits policy-driven allocation strategies based on application privilege levels and data level prioritization metrics (e.g., utilization) to efficiently manage the on-chip memory real-estate. Our experimental results on Mediabench/CHStone benchmarks running on various Chip-Multiprocessor configurations and software stacks (RTOS, virtualization, secure execution) showed that SPMVisor enhances performance by 71 % on average and reduces power consumption by 79 % on average with respect to traditional context switching schemes. We showed the benefits of using vSPMs in a various environments (a RTOS multi-tasking environment, a virtualization environment, and a trusted execution environment). Furthermore, we explored the effects of mapping instructions and data onto vSPMs, and showed that sharing on-chip space reduces both execution time and energy by an average 16 % and 12 % respectively. We then compared our priority-driven memory allocation scheme with traditional dynamic allocation and showed an average 54 % execution time reduction and 65 % energy savings. Finally, to further validate the SPMVisor’s benefits, we modified the initial bus-based architecture to include a mesh-based CMP with up to 4×4 nodes. We were able to observe that SPMVisor’s priority-driven allocator was able to reduce execution time by an average 17 % with respect to competing allocation policies, while saving an average 65 % across various architectural configurations. We were also able to observe that SPMVisor reduces execution time by an average 12.6 % with respect to competing allocation policies, while saving an average 63.5 % in total energy for various architectural configuration running 1024 jobs.

Compiler support for lightweight context switching

We propose a new language-neutral primitive for the LLVM compiler, which provides efficient context switching and message passing between lightweight threads of control. The primitive, called Swapstack, can be used by any language implementation based on LLVM to build higher-level language structures such as continuations, coroutines, and lightweight threads. As part of adding the primitives to LLVM, we have also added compiler support for passing parameters across context switches. Our modified LLVM compiler produces highly efficient code through a combination of exposing the context switching code to existing compiler optimizations, and adding novel compiler optimizations to further reduce the cost of context switches. To demonstrate the generality and efficiency of our primitives, we add one-shot continuations to C++, and provide a simple fiber library that allows millions of fibers to run on multiple cores, with a work-stealing scheduler and fast inter-fiber sychronization. We argue that compiler-supported lightweight context switching can be significantly faster than using a library to switch between contexts, and provide experimental evidence to support the position.

Survey of Real Time Scheduling Algorithms

Real-Time systems are becoming pervasive. In a Real-Time System the correctness of the system behavior depends not only on the logical results of the computations, but also on the physical instant at which these results are produced. A missed deadline in hard real-time systems is catastrophic and in soft real-time systems it can lead to a significant loss .This work talks about static and dynamic scheduling algorithms for real time task. The problem of real-time scheduling spans a broad spectrum of algorithms from simple uniprocessor to highly sophisticated multiprocessor scheduling algorithms which are priority driven and divided into three classes fixed priority, dynamic priority and hybrid priority. Finally conclusion shows that Instantaneous utilization factor scheduling Algorithm gives better result in uniprocessor scheduling algorithms and Modified Instantaneous utilization factor scheduling Algorithm gives better context switching, response time and CPU utilization as compared to previous scheduling algorithms. Keywords- Deadline, Laxity, Utilization, Precedence, context switching.

PS-TLB

Traversing the page table during virtual to physical address translation causes pipeline stalls when misses occur in the translation-lookaside buffer (TLB). State-of-the-art translation proposals typically optimize a single aspect of translation performance (e.g., translation sharing, context switch performance, etc.) with potential trade-offs of additional hardware complexity, increased translation latency, or reduced scalability. In this article, we propose the partial sharing TLB (PS-TLB), a fast and scalable solution that reduces off-chip translation misses without sacrificing the timing-critical requirement of on-chip translation. We introduce the partial sharing buffer (PSB) which leverages application page sharing characteristics using minimal additional hardware resources. Compared to the leading TLB proposal that leverages sharing, PS-TLB provides a more than 45% improvement in translation latency with a 9% application speedup while using fewer storage resources. In addition, the page classification and PS-TLB architecture provide further optimizations including an over 30% reduction of interprocessor interrupts for coherence, and reduced context switch misses with fewer resources compared with existing methods.

Traffic Square Management System

If the traffic is more on one side and less on other side so there all way a waste of time and fuel on the traffic signal. Which is serious problem now day so there an need to have an intelligent traffic system which can detect the amount of traffic and make the change accordingly by using sensor and tranducer. Also by using motion detection camera at the lane we can find out the vehicle owner who break the traffic rules at the signal. Keywords: ANPR,Scheduling OCR, DIP, Context switch, IR Radiation,TSOP

A Multi–Alphabet Arithmetic Coding Hardware Implementation for Small FPGA Devices

Arithmetic coding is a lossless compression algorithm with variable-length source coding. It is more flexible and efficient than the well-known Huffman coding. In this paper we present a non-adaptive FPGA implementation of a multi-alphabet arithmetic coding with separated statistical model of the data source. The alphabet of the data source is a 256-symbol ASCII character set and does not include the special end-of-file symbol. No context switching is used in the proposed design which gives maximal throughput without pipelining. We have synthesized the design for Xilinx FPGA devices and used their built-in hardware resources.

클라우드 자원 브로커에서 확장성 있는 가상 머신 할당 기법을 이용한 비용 적응형 작업 스케쥴링 알고리즘

사용자들은 자신의 작업을 처리하기 위해 자신에게만 한정된 가상 컴퓨팅 자원을 클라우드 서비스 제공자로부터 할당 받아 타 사용자로부터 독립된 환경에서 작업을 처리하게 된다. 이를 자동화된 방법으로 최적화를 대신 수행해주기 위한 모델로 브로커 미들웨어가 제시되었고 마감시간을 만족하는 이내에서 자원 이용률을 높이는 접근법으로 필요 가상 머신의 숫자를 줄여 비용을 절약한다. 이를 다루는 많은 논문들에서 작업 스케줄링은 기존 사용자들간의 독립을 보장하여 하나의 가상 머신이 하나의 작업에 한정된 가상 머신에서 처리하는 방식으로 다루어지고 있다. 하지만 기존의 SRSV 방식에서는 높은 정도의 다중 프로그래밍 작업이 아닐 경우 시스템을 효율적으로 사용하지 못한다. 이에 본 논문에서는 해당 자원을 마감시간과 스래싱(thrashing), 문맥 전환(context switching)에 따른 성능 저하를 고려한 상태에서 다중 프로그래밍 정도를 높여 낭비되는 자원을 최소화하여 비용을 절약하려고 한다. 실험 결과를 통해 제안하는 방법이 제약조건 이내에서 기존의 방식에 비해 좀 더 좋은 가격 대비 성능을 가지는 것을 보인다. Cloud service users request dedicated virtual computing resource from the cloud service provider to process jobs in independent environment from other users. To optimize this process with automated method, in this paper we proposed a framework for workflow scheduling in the cloud environment, in which the core component is the middleware called broker mediating the interaction between users and cloud service providers. To process jobs in on-demand and virtualized resources from cloud service providers, many papers propose scheduling algorithms that allocate jobs to virtual machines which are dedicated to one machine one job. With this method, the isolation of being processed jobs is guaranteed, but we can't use each resource to its fullest computing capacity with high efficiency in resource utilization. This paper therefore proposed a cost-efficient job scheduling algorithm which maximizes the utilization of managed resources with increasing the degree of multiprogramming to reduce the number of needed virtual machines; consequently we can save the cost for processing requests. We also consider the performance degradation in proposed scheme with thrashing and context switching. By evaluating the experimental results, we have shown that the proposed scheme has better cost-performance feature compared to an existing scheme.

Fast and low overhead architectural transaction level modelling for large-scale network-on-chip simulation

Early system modelling is an essential tool to accelerate software development, architectural analysis and hardware verification in complex many-core system-on-chips (SoCs). Transaction level modelling (TLM) offers a higher level of abstraction than register transfer level (RTL) and can be used for early system modelling. Maintaining simulation speed with the right accuracy is a major challenge and this paper proposes SystemC-based architectural modelling techniques that extend TLM to deliver faster simulation models for many-core system. The proposed approach considers a micro-scheduler for large modules (in the sense of SystemC modules) to locally manage all events in the module. Exploiting this micro-scheduler along with function object and coroutine concepts, the authors propose a lightweight thread process that significantly reduces the context switching overhead among the different processes. Additionally the micro-scheduler allows some processes to be run ahead of simulation time. The proposed techniques are applied to the model of a very large networks-on-chip (NoC) formed by thousands of cores stressing the simulation capabilities of the host computer and operating system. The experimental results demonstrate that the model can run successfully and exhibits up to 93% improvement in simulation speed compared to traditional SystemC-based modelling.

LEAN

Debugging concurrent programs is known to be difficult due to scheduling non-determinism. The technique of multiprocessor deterministic replay substantially assists debugging by making the program execution reproducible. However, facing the huge replay traces and long replay time, the debugging task remains stunningly challenging for long running executions. We present a new technique, LEAN, on top of replay, that significantly reduces the complexity of the replay trace and the length of the replay time without losing the determinism in reproducing concurrency bugs. The cornerstone of our work is a redundancy criterion that characterizes the redundant computation in a buggy trace. Based on the redundancy criterion, we have developed two novel techniques to automatically identify and remove redundant threads and instructions in the bug reproduction execution. Our evaluation results with several real world concurrency bugs in large complex server programs demonstrate that LEAN is able to reduce the size, the number of threads, and the number of thread context switches of the replay trace by orders of magnitude, and accordingly greatly shorten the replay time.

Towards efficient GPU sharing on multicore processors

Scalable systems employing a mix of GPUs with CPUs are becoming increasingly prevalent in high-performance computing. The presence of such accelerators introduces significant challenges and complexities to both language developers and end users. This paper provides a close study of efficient coordination mechanisms to handle parallel requests from multiple hosts of control to a GPU under hybrid programming. Using a set of microbenchmarks and applications on a GPU cluster, we show that thread and process-based context hosting have different tradeoffs. Experimental results on application benchmarks suggest that both thread-based context funneling and process-based context switching natively perform similarly on the latest Fermi GPUs, while manually guided context funneling is currently the best way to achieve optimal performance.

IGPU

Since the introduction of fully programmable vertex shader hardware, GPU computing has made tremendous advances. Exception support and speculative execution are the next steps to expand the scope and improve the usability of GPUs. However, traditional mechanisms to support exceptions and speculative execution are highly intrusive to GPU hardware design. This paper builds on two related insights to provide a unified lightweight mechanism for supporting exceptions and speculation on GPUs. First, we observe that GPU programs can be broken into code regions that contain little or no live register state at their entry point. We then also recognize that it is simple to generate these regions in such a way that they are idempotent, allowing their entry points to function as program recovery points and enabling support for exception handling, fast context switches, and speculation, all with very low overhead. We call the architecture of GPUs executing these idempotent regions the iGPU architecture. The hardware extensions required are minimal and the construction of idempotent code regions is fully transparent under the typical dynamic compilation framework of GPUs. We demonstrate how iGPU exception support enables virtual memory paging with very low overhead (1% to 4%), and how speculation support enables circuit-speculation techniques that can provide over 25% reduction in energy.

Task-Centered Context Manager for Customer Relationship Management Systems

In the customer relationship management (CRM) environment, agents tend to multitask. But the current CRM systems are not task-centered and therefore hinder the agent’s multitasking performance. We proposed the task-centered context manager, which better matches the agent’s mental model by focusing on the tasks that an agent is working on. The task-centered context manager automatically creates contexts, each for a separate task. It provides a flexible context switching mechanism for agents to easily go back and forth between tasks. And its priority-driven interface helps agents focus on important tasks. A formative usability evaluation indicated that our task-centered context manager was very well received by participating agents as evidenced by the overall System Usability Scale score of 88.5.

Model checking Trampoline OS: a case study on safety analysis for automotive software

SUMMARY Model checking is an effective technique used to identify subtle problems in software safety using a comprehensive search algorithm. However, this comprehensiveness requires a large number of resources and is often too expensive to be applied in practice. This work strives to find a practical solution to model-checking automotive operating systems for the purpose of safety analysis, with minimum requirements and a systematic engineering approach for applying the technique in practice. The paper presents methods for converting the Trampoline kernel code into formal models for the model checker SPIN, a series of experiments using an incremental verification approach, and the use of embedded C constructs for performance improvement. The conversion methods include functional modularization and treatment for hardware-dependent code, such as memory access for context switching. The incremental verification approach aims at increasing the level of confidence in the verification even when comprehensiveness cannot be provided because of the limitations of the hardware resource. We also report on potential safety issues found in the Trampoline operating system during the experiments and present experimental evidence of the performance improvement using the embedded C constructs in SPIN. Copyright © 2012 John Wiley & Sons, Ltd.

Preserving the original MPI semantics in a virtualized processor environment

Processor virtualization is a technique in which a programmer divides a computation into many entities, which are mapped to the available processors. The number of these entities, referred to as virtual processors, is typically larger than the number of physical processors. For an MPI program, the user decomposes the computation into more MPI tasks than physical processors. This approach allows overlapping computation and communication, and enables load balancing. User-level threads are often used to implement these virtual processors because they are generally faster to create, manage and migrate than heavy processes or kernel threads. However, these threads present issues concerning private data because they break the private address space assumption typically made by MPI programs. In this paper, we propose a new approach to privatize data in user-level threads. This approach is based on thread-local storage (TLS), which is often used by kernel threads. We apply this technique so that MPI programs can be executed in a virtualized environment while preserving their original semantics. We show that this alternative has a more efficient context switch and lower migration cost and is simpler to implement than other approaches.

Context-Induced Relapse to Alcohol Seeking After Punishment in a Rat Model

Rat studies have demonstrated that exposure to environments associated with alcohol intake reinstates alcohol seeking after extinction of alcohol-reinforced responding in a different context. However, extinction is limited as an abstinence model, because humans typically abstain because of negative consequences associated with excessive drinking. It is currently unknown whether alcohol-associated contexts can provoke relapse to alcohol seeking after alcohol-taking behavior is suppressed by adverse consequences in a different context. Alcohol-preferring P rats were first given home-cage access to 20% ethanol. Next, they were trained to self-administer 20% ethanol in one context (context A). Subsequently, all rats continued to self-administer alcohol in a different context (context B). For one group, 50% of alcohol-reinforced responses were punished by mild footshock; two other groups either received noncontingent shocks or no shock. A fourth group was given extinction training in context B. All rats were then tested for relapse to alcohol seeking under extinction conditions in contexts A and B. In Context B, alcohol-taking behavior was suppressed by contingent shock (punishment) and extinction training but not by noncontingent shock. In Context A, relapse to alcohol seeking was reliably observed in the punished and extinction groups; a context switch had no effect on alcohol seeking in the no-shock or noncontingent shock groups. Our data indicate that punishment-induced suppression of alcohol-taking behavior is context-dependent. We propose that our procedure can be used to explore mechanisms of context-induced relapse to alcohol seeking after alcohol-taking behavior is suppressed by adverse consequences.

Global EDF-Based On-Line Energy-Aware Real-Time Scheduling Algorithm in Multi-Core Systems

PDF HTML阅读 XML下载 导出引用 引用提醒 多核系统中基于Global EDF 的在线节能实时调度算法 DOI: 10.3724/SP.J.1001.2012.04054 作者: 作者单位: 作者简介: 通讯作者: 中图分类号: 基金项目: 国家教育部博士点基金(20104307110005); 湖南省优秀研究生创新资助(CX2010B026); 国防科学技术大学优秀研究生创新资助(B100601) Global EDF-Based On-Line Energy-Aware Real-Time Scheduling Algorithm in Multi-Core Systems Author: Affiliation: Fund Project: 摘要 | 图/表 | 访问统计 | 参考文献 | 相似文献 | 引证文献 | 资源附件 | 文章评论 摘要:随着多核系统能耗问题日益突出,在满足时间约束条件下降低系统能耗成为多核实时节能调度研究中亟待解决的问题之一.现有研究成果基于事先已知实时任务属性的假设,而实际应用中,只有当任务到达之后才能够获得其属性.为此,针对一般任务模型,不基于任何先验知识,提出一种多核系统中基于Global EDF 在线节能硬实时任务调度算法,通过引入速度调节因子,利用松弛时间,结合动态功耗管理和动态电压/频率调节技术,降低多核系统中任务的执行速度,达到实时约束与能耗节余之间的合理折衷.所提出的算法仅在上下文切换和任务完成时进行动态电压/频率调节,计算复杂度小,易于在实时操作系统中实现.实验结果表明,该算法适用于不同类型的片上动态电压/频率调节技术,节能效果始终优于Global EDF 算法,最多可节能15%~20%,最少可节能5%~10%. Abstract:As the energy consumption of multi-core systems becomes increasingly prominent, meeting the time constraints while reducing as much as possible system energy consumption is still an urgent problem in real-time energy-aware scheduling in multi-core system. Most existing works have assumptions on priori information of real-time tasks, but in real applications the tasks’ property be received only when the tasks arrive. Therefore, based on the general task model with no priori to tasks’ properties, this paper proposes a global EDF-based on-line energy-aware scheduling algorithm for hard real-time tasks in multi-core system. The proposed algorithm can reduce the execution speed of task in multi-core system and reach a reasonable compromise between real-time constraints and energy savings, as it introduces a speed scale factor for utilizing the slack time and combines dynamic power management with dynamic voltage/frequency scaling techniques. The algorithm implements dynamic voltage/frequency scaling only in each context switch time and task completion time, with the smaller computational complexity, and easier to be included in real-time operating system. Experimental results show that the algorithm can be well applied to different kinds of dynamic voltage/frequency scaling on chip, and compared with Global EDF algorithm, it gain more energy savings in all cases, which can improve energy savings about 15% to 20% at most and about 5% to 10% at least. 参考文献 相似文献 引证文献