Context Switching Research Articles

The impact of context processing deficits on task-switching performance in schizophrenia

The prefrontal cortex (PFC) has been described as important for maintaining and implementing contextual information in the service of goal-oriented behavior. Accordingly, impairments in context processing are thought to underlie cognitive deficits associated with schizophrenia, a clinical disorder that has been linked to PFC dysfunction (Servan-Schreiber et al., 1996). However, task switching, a cognitive ability linked to PFC function, has not been consistently impaired in schizophrenia. In this experiment, we assessed whether task-switching performance would be selectively impaired for patients when context demands were high. In the rule-switching condition, a switch required the updating of the relevant task response rules whereas perceptual switching did not entail a switching of contextual information. Instead, a perceptual switch entailed a shift of visuospatial attention to the relevant feature. A second goal was to determine whether potential deficits in context switching would be observed in schizophrenia even in situations when these patients do not need to overcome a prepotent response. Studies of context processing have typically required patients with schizophrenia to use contextual rules to overcome prepotent response tendencies whereas our switching paradigm did not require the inhibition of a competing response. Patients were much slower to switch tasks than controls when contextual rules switched from one trial to the next whereas their performance was intact when the switch occurred between different feature sets and contextual demands were low. Our results demonstrate that context processing deficits are observable in schizophrenia even when there is no prepotent response tendency to inhibit. Moreover, our results suggest that PFC impairments influence performance primarily when patients are required to switch the application of one explicit rule to another.

Cell Broadband Engine processor performance optimization: Tracing tools implementation and use

Optimizing performance on multicore processors is a daunting task M. S. Chang because of the increased importance of such factors as thread communication, memory contention, and memory access latency. This paper presents two tools that programmers and performance analysts can use to understand application performance on the Cell Broadband Engine® (Cell/B.E.) processor: the Performance Debugging Tool (PDT) and the Trace Analyzer (TA). PDT traces user-space events, augmenting them with scheduling data from the operating system; those traces are then read, analyzed, and presented visually by the TA. This paper describes the implementation issues arising from the fact that a common lowoverhead clock shared by all cores, essential for analysis and visualization, is not available on the Cell/B.E. processor. The TA employs an offline analysis to align the collected events to a common time based only on thread-local timestamps, event order, and context switch information. We also discuss the overhead of tracing and its impact on execution and performance analysis. We illustrate the use of the PDT and TA by analyzing several significant Cell/B.E. processor workloads, including native code and higher-level abstractions offered by the Data Communication and Synchronization services. We show how trace analysis can help identify performance issues in these workloads and how it can be used by programmers to spot performance antipatterns (common programming practices leading to suboptimal performance).

Exploiting the parallelism of multidimensional wave digital algorithms on multicore computers

Multidimensional wave digital algorithms for numerical integration of partial differential equations exhibit not only important robustness properties, but also a massive amount of parallelism. As the technology limit of heat dissipation stalls a further increase of clock rates, modern CPUs incorporate multiple cores for parallel computation. In this paper, a safe and efficient multithreading concept is presented to exploit the multicore architecture for multidimensional wave digital algorithms. Context switching and synchronization overhead is investigated as well as effects of unfair operating system thread scheduling due to unequal cache sharing of cores. Simulation results for the nonlinear Euler equations confirm the efficiency of the proposed setup on a 1-core, 4-core and a 2 × 4-core system.

Synchronizing Redundant Cores in a Dynamic DMR Multicore Architecture

We introduce the difficulties in processing context switches, exceptions, and interrupts in DMR architectures. We propose ways to address these problems in a dynamic DMR (DDMR) architecture, providing methods that assure both cores detect the event, synchronize it to the same instruction, perform a secure context switch, run correct interrupt service routines, and avoid process termination. DDMR uses a time-division multiplexing (TDM) ring architecture to dynamically connect pairs of cores. We enhance this protocol to include the different message types required to handle interrupts and exceptions. We also propose a more efficient address-based, rather than TDM-based, ring architecture.

HTM design spaces

This paper proposes a Hardware Transactional Memory (HTM) design for multi-core environments. Using a novel technique to keep track of transactional read-write entries, the design provides a holistic and scalable solution to Transactional Memory (TM) implementation issues of context switching, process migration and overflow handling. Another aspect of the design is that it allows transactions to run in a highly concurrent manner by using special techniques to handle conflict resolution, conflict detection and overflows. The feasibility and validity of the proposed design are demonstrated by developing a synthesizable Hardware Description Language (HDL) model of the design and also experimenting on the same with standard benchmarks.

Split-Belt Treadmill Adaptation Transfers to Overground Walking in Persons Poststroke

Background and Objective. Following stroke, subjects retain the ability to adapt interlimb symmetry on the split-belt treadmill. Critical to advancing our understanding of locomotor adaptation and its usefulness in rehabilitation is discerning whether adaptive effects observed on a treadmill transfer to walking over ground. We examined whether aftereffects following split-belt treadmill adaptation transfer to overground walking in healthy persons and those poststroke. Methods. Eleven poststroke and 11 age-matched and gender-matched healthy subjects walked over ground before and after walking on a split-belt treadmill. Adaptation and aftereffects in step length and double support time were calculated. Results. Both groups demonstrated partial transfer of the aftereffects observed on the treadmill (P < .001) to overground walking ( P < .05), but the transfer was more robust in the subjects poststroke (P < .05). The subjects with baseline asymmetry after stroke improved in asymmetry of step length and double limb support (P = .06). Conclusions. The partial transfer of aftereffects to overground walking suggests that some shared neural circuits that control locomotion for different environmental contexts are adapted during split-belt treadmill walking. The larger adaptation transfer from the treadmill to overground walking in the stroke survivors may be due to difficulty adjusting their walking pattern to changing environmental demands. Such difficulties with context switching have been considered detrimental to function poststroke. However, we propose that the persistence of improved symmetry when changing context to overground walking could be used to advantage in poststroke rehabilitation.

Certifying Low-Level Programs with Hardware Interrupts and Preemptive Threads

Hardware interrupts are widely used in the world's critical software systems to support preemptive threads, device drivers, operating system kernels, and hypervisors. Handling interrupts properly is an essential component of low-level system programming. Unfortunately, interrupts are also extremely hard to reason about: they dramatically alter the program control flow and complicate the invariants in low-level concurrent code (e.g., implementation of synchronization primitives). Existing formal verification techniques--including Hoare logic, typed assembly language, concurrent separation logic, and the assume-guarantee method--have consistently ignored the issues of interrupts; this severely limits the applicability and power of today's program verification systems. In this paper we present a novel Hoare-logic-like framework for certifying low-level system programs involving both hardware interrupts and preemptive threads. We show that enabling and disabling interrupts can be formalized precisely using simple ownership-transfer semantics, and the same technique also extends to the concurrent setting. By carefully reasoning about the interaction among interrupt handlers, context switching, and synchronization libraries, we are able to--for the first time--successfully certify a preemptive thread implementation and a large number of common synchronization primitives. Our work provides a foundation for reasoning about interrupt-based kernel programs and makes an important advance toward building fully certified operating system kernels and hypervisors.

A fast computational algorithm for simulating round-robin service

An efficient computation-based algorithm for effecting round-robin (RR) service in discrete-event simulation systems is presented. The new algorithm improves upon an older computational algorithm which itself is an improvement over naive RR scheduling currently in use in process-oriented simulation systems. The naive approach can be prohibitively expensive due to process context switch overhead. The original computational algorithm avoids much of this context switching but offers a run-time complexity of only O(n2), where n is the size of the job pool. This is because the processing of each arrival and departure event requires a traversal of the entire pool. In this paper, we propose an improved algorithm which reduces run-time complexity to O(n log n) by using tree-based data structures. The expected computation to process each arrival or departure event is proportional to O(log n). Empirical evidence suggests that, except for very small size of job pool, this algorithm is considerably faster than other methods.

Cross-layer customization for rapid and low-cost task preemption in multitasked embedded systems

Preemptive multitasking is widely used in many low-cost and real-time embedded applications for its superior hardware utilization. The frequent and asynchronous context switches, however, require the preservation and restoration of the task state, thus resulting in a large number of memory transfer instructions. As a consequence, task responsiveness and application throughput can be significantly deteriorated. To address this problem we propose a cross-layer customization framework which through the close cooperation of compiler, OS, and hardware architecture achieves rapid and low-cost task switch. Application information extracted during compile-time regarding state liveness is exploited in order to preserve a minimal amount of task state on task preemption. We introduce two complementary techniques to implement the application-aware state preservation. The first technique utilizes compiler-generated custom routines which preserve/restore an extremely small live context at judiciously selected points in the application code. The second technique requires more sophisticated hardware support. It employs an OS-controlled register file mapping to achieve a rapid context switch. By mapping a small fraction of the register file in a single clock cycle, a context switch is achieved requiring no memory transfers for the majority of cases to preserve/restore the live state. The effect of aggressively replicated register files, where each task is given its own replica, is achieved with the hardware cost of only adding from 25% to 50% extra physical registers. Through the utilization of these novel mechanisms, a significant improvement on task response time is achieved as the context-switch cost is minimized.

Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture

This paper presents a novel architecture to increase the hardware utilization in multi-context field programmable gate arrays (MC-FPGAs). Conventional MC-FPGAs use dedicated tracks to transfer context-ID bits. As a result, hardware utilization ratio decreases, since it is very difficult to map different contexts, area efficiently. It also increases the context switching power, area and static power of the context-ID tracks. The proposed MC-FPGA uses the same wires to transfer both data and context-ID bits from cell to cell. As a result, programs can be mapped area efficiently by partitioning them into different contexts. An asynchronous multi-context logic block architecture to increase the processing speed of the multiple contexts is also proposed. The proposed MC-FPGA is fabricated using 6-metal 1-poly CMOS design rules. The data and context-ID transfer delays are measured to be 2.03ns and 2.26ns respectively. We achieved 30% processing time reduction for the SAD based correspondance search algorithm.

Modeling and analysis of core-centric network processors

Network processors can be categorized into two types, the coprocessors-centric model in which the data-plane is handled by coprocessors, and the core-centric model in which the core processes most of the data-plane packets yet offloading some tasks to coprocessors. While the former has been properly explored over various applications, researches regarding the latter remain limited. Based on the previous experience of prototyping the virtual private network (VPN) over the IXP425 network processor, this work aims to derive design implications for the core-centric model performing computational intensive applications. From system and IC vendors' perspectives, the continuous-time Markov chain and Petri net simulations are adopted to explore this architecture. Analytical results prove to be quite inline with those of the simulation and implementation. With subsequent investigation we find that appropriate process run lengths can improve the effective core utilization by 2.26 times, and by offloading the throughput boosts 7.5 times. The results also suggest single process programming since context switch overhead impacts considerably on the performance.

Partial reinforcement and context switch effects in human predictive learning

Human participants were trained in a trial-by-trial contingency judgements task in which they had to predict the probability of an outcome (diarrhoea) following different cues (food names) in different contexts (restaurants). Cue P was paired with the outcome on half of the trials (partial reinforcement), while cue C was paired with the outcome on all the trials (continuous reinforcement), both cues in Context A. Test was conducted in both Context A and a different but equally familiar context (B). Context change decreased judgements to C, but not to P (Experiment 1). This effect was found only in the cue trained in the context where a different cue was partially reinforced (Experiment 2). Context switch effects disappeared when different cues received partial reinforcement in both contexts of training (Experiment 3). The implications of these results for an explanation of context switch effects in terms of ambiguity in the meaning of the cues prompting attention to the context (e.g., Bouton, 1997) are discussed.

Catching two rabbits: adaptive real‐time support for embedded Linux

AbstractThe trend of digital convergence makes multitasking common in many digital electronic products. Some applications in those systems have inherent real‐time properties, while many others have few or no timeliness requirements. Therefore the embedded Linux kernels, which are widely used in those devices, provide real‐time features in many forms. However, providing real‐time scheduling usually induces throughput degradation in heavy multitasking due to the increased context switches. Usually the throughput degradation becomes a critical problem, since the performance of the embedded processors is generally limited for cost, design and energy efficiency reasons. This paper proposes schemes to lessen the throughput degradation, which is from real‐time scheduling, by suppressing unnecessary context switches and applying real‐time scheduling mechanisms only when it is necessary. Also the suggested schemes enable the complete priority inheritance protocol to prevent the well‐known priority inversion problem. We evaluated the effectiveness of our approach with open‐source benchmarks. By using the suggested schemes, the throughput is improved while the scheduling latency is kept same or better in comparison with the existing approaches. Copyright © 2008 John Wiley &amp; Sons, Ltd.

Fast-path I/O architecture for high performance streaming server

In a disk-network scenario where expensive data transfers are the norm, such as in multimedia streaming applications, for example, a fast-path I/O architecture is generally considered to be "good practice." Here, I/O performance can be improved through minimizing the number of in-memory data movements and context switches. In this paper, we report the results of the design and implementation of a high-performance streaming server using cheap hardware units assembled directly on a test card (i.e., NS card). The hardware part of our architecture is open to further reuse, extension, and integration with other applications even in the case of inexpensive and/or faster hardware. From the viewpoint of software-aided I/O, we offer Stream Disk Array (SDA) for scatter/gather-style block I/O, EXT3NS multimedia file system for large-scale file I/O, and interoperable streaming server for stream I/O.

Reducing the TLB Context Switching Miss Ratio With Banked and Prefetching Mechanism

Address translations from virtual addresses to physical addresses are widely considered as one of the most important issue for memory system performance. In order to improve the performance, the Translation Lookaside Buffer (TLB) is used. Lots of different methodologies are proposed to reduce TLB misses. Most designs just simply try to increase the total size of their TLBs to reduce the capacity misses or just simply use the fully associativity to reduce the conflict misses. Furthermore, some designs even try to incorporate the operating system (OS) and TLBs with very complex methods. Only some studies consider influence of performance on the context switching issue. Most traditional designs just simply added some types of address space identifier within the TLB tags. Nevertheless, the worse case of all is the x86 architecture which flushes all its TLB entries on context switching. This paper proposes a banked TLB structure with prefetching mechanism to reduce the miss rate in context switching for 32K page size. All simulations were done with modified SimpleScalar 3.0d tool suite and SPEC95 benchmarks. The results show that the proposed mechanism can provide acceptable performance improvement than the worse case x86 style design. The miss rate may even be only 1/10 or less. Thus, the proposed architecture may be suitable to be implemented inside processors to reduce the context switching misses. Furthermore, we'll try to implement it inside our new asynchronous processor.

Input–output plasticity of peripheral responses in cerebellar Golgi cells in vivo

In this issue of The Journal of Physiology, Xu & Edgley (2008) report on the induction of plastic changes in the response to peripheral stimulation in one of the major cerebellar cortical neurons, the Golgi cell. The response plasticity is induced by peripheral stimulation in combination with climbing fibre activation, but not by the same peripheral stimulation alone. Hence, this is a new form of climbing fibre-dependent cerebellar plasticity, which adds to the previously described long-term depression of parallel fibre input to Purkinje cells (Ito, 2006) and long-term potentiation of parallel fibre input to molecular layer interneurons (Jorntell & Ekerot, 2003; Rancillac & Crepel, 2004; Ito, 2006). Papers from this lab have earlier reported on a peculiar peripheral response in Golgi cells located in crus I/II of the rat (Holtzman et al. 2006b). This response is a relatively long-lasting depression of spike activity which seems to be evoked from the skin of all four limbs as well as the snout. In addition, muscle afferents in the group II/group III range also activate this response, which is transmitted via the anterolateral system bilaterally (Holtzman et al. 2006a). It is very different from the more straightforward excitatory responses (presumed to be mossy fibre–Golgi cell and/or mossy fibre–granule cell–Golgi cell responses) that have been described for Golgi cells by other authors (Vos et al. 1999; Jorntell & Ekerot, 2006). Nevertheless, this is a very consistent phenomenon, which in the hands of this lab in principle works as a diagnostic criterion for a Golgi cell recording. Interestingly, in this paper (Xu & Edgley, 2008) the authors show that a similar inhibitory response in Golgi cells can be evoked also after climbing fibre activation. However, this inhibitory response is not mediated by the same pathway as the peripherally induced inhibitory response since the peripheral stimulation evoked no climbing fibre responses in the local Purkinje cells. The inhibitory responses could be evoked by other cerebellar inhibitory neurons which are activated by climbing fibres and/or peripheral inputs, i.e. basket cells/stellate cells (Jorntell & Ekerot, 2003; Szapiro & Barbour, 2007), Purkinje cells and Lugaro cells (Dumoulin et al. 2001). Alternatively, inhibitory responses could be induced via special types of extrasynaptic receptors on Golgi cells, which would be activated by spill-over of glutamate from climbing fibres and/or peripheral afferent pathways. However, the major new finding of this paper is that after conjunctive peripheral and climbing fibre activation for 20 min, the inhibitory responses evoked from the periphery are persistently reduced. Naturally, this could be explained by a long-lasting depression of the efficacy at the inhibitory synapse(s) on the Golgi cell. Alternatively, the depression could be the result of a reduced excitatory synaptic input to the presynaptic inhibitory cell. A third possibility would be changes to the efficacy of the extrasynaptic receptors. To provide a better clue about the locus/loci of plasticity, these experiments should ideally be repeated whilst recording from the other types of neurons. This finding adds to recent literature that the cerebellum is highly prone to plastic changes in vivo. Of course, the functional consequences of this form of plasticity depend on the function of the Golgi cells. Recent in vivo recordings from their main postsynaptic targets, the granule cells, indicated that fast inhibitory responses are virtually lacking in the adult, non-anaesthetized animal, suggesting that the inhibitory granule cell control from Golgi cells may be primarily exerted on a long time scale (Jorntell & Ekerot, 2006), possibly related to overall context switching. This function seem to be in agreement with findings from a recent series of experiments from this laboratory, which shows us that Golgi cells are highly sensitive to inputs from a system that is traditionally viewed as being involved in arousal (Holtzman et al. 2006a). This system induces relatively long-lasting changes in Golgi cell excitability, the magnitude of which can be changed via climbing fibre-dependent plasticity (Xu & Edgley, 2008).

A context switching streaming memory architecture to accelerate a neocortex model

A novel architecture to accelerate a neocortex inspired cognitive model is presented. The architecture utilizes a collection of context switchable processing elements (PEs). This enables time multiplexing of nodes in the model onto available PEs. A streaming memory system is designed to enable high-throughput computation and efficient use of memory resources. Several scheduling algorithms were examined to efficiently assign network nodes to the PEs. Multiple parallel FPGA-accelerated implementations were evaluated on a Cray XD1. Networks of varying complexity were tested and indicate that hardware acceleration can provide an average throughput gain of 184 times over equivalent parallel software implementations.

Recency and primacy in causal judgments: Effects of probe question and context switch on latent inhibition and extinction

Traditional associative models assume that associative weights are updated on a trial-by-trial basis. As a result, it is usually expected that responses based on these weights will tend to reflect the most recently presented contingencies. However, a number of studies of human causal judgments have shown primacy effects, wherein judgments obtained at the end of a series of trials are more strongly influenced by a contingency that was in force early in the sequence than by a contingency that was in force later in the sequence. The experiments described in this article replicated other work showing that requesting causal judgments during a sequence can reverse primacy and produce strong recency effects. Evidence was also obtained to suggest that primacy effects are produced by an interaction between latent inhibition and extinction processes and that requesting a judgment affects both of these processes.

PipesFS

This paper presents PipesFS, an I/O architecture for Linux 2.6 that increases I/O throughput and adds support for heterogeneous parallel processors by (1) collapsing many I/O interfaces onto one: the Unix pipeline, (2) increasing pipe efficiency and (3) exploiting pipeline modularity to spread computation across all available processors. PipesFS extends the pipeline model to kernel I/O and communicates with applications through a Linux virtual filesystem (VFS), where directory nodes represent operations and pipe nodes export live kernel data. Users can thus interact with kernel I/O through existing calls like mkdir, tools like grep, most languages and even shell scripts. To support performance critical tasks, PipesFS improves pipe throughput through copy, context switch and cache miss avoidance. To integrate heterogeneous processors (e.g., the Cell) it transparently moves operations to the most efficient type of core.

From the Office to the Pub: The Role of Smoking-Relevant Contexts and Cue-Elicited Urge to Smoke

The present study investigates how environmental contexts can affect cue-elicited urge to smoke. A total of 33 smokers were repeatedly presented with a cue predicting smoking and a cue predicting no smoking in one room and the effect of context change in a different room was assessed. Results endorsed earlier findings that a cue predicting smoking availability elicited more urge to smoke than a cue predicting smoking unavailability. Furthermore, this study shows that a context switch from a low smoking-relevant room to a high smoking-relevant room reduces the learned differential urge responding between the two availability cues. These findings are discussed in relation to the role that smoking-relevant contexts play in the generalization of differential urge responding after a context switch. Furthermore, implications for government policies on smoking and clinical issues are discussed.