Consecutive Test Patterns Research Articles

A Novel Test Pattern Optimization Method Using Recurrent Neural Network

Testing modern integrated circuit (IC) is challenging with introduction of System-on Chip (SOC). Enormous test pattern count is required to authenticate the IC which inflates power consumption. Henceforth, it is mandatory to incorporate power minimization techniques at circuit design phase. Optimizing test patterns is one such effective technique that curtails test power without altering circuit design. In this paper, a new test pattern reordering algorithm is proposed based on Recurrent Neural Network. Hopfield Neural Network (HNN) constitutes an optimized solution for solving traveling salesman problem (TSP). Since, test pattern reordering can be interpreted as TSP, optimized test pattern order is attained with HNN. Energy function of this algorithm falls into local minimum, so to eradicate this issue, the algorithm is modified. Test patterns are reordered with minimal hamming distance among consecutive test patterns. The proposed algorithm is implemented in ISCAS’89 Sequential Benchmark circuits. Experimental results prove that significant reduction in transition count is accomplished with proposed algorithm without compromising fault coverage.

Two-stage low power test data compression for digital VLSI circuits

In this paper, we present a hybrid X-filling and two-stage test data compression (TS-TDC) techniques for digital VLSI circuits to reduce the test power and test data volume respectively. The proposed hybrid X-filling combines adjacent filling and modified 4m filling technique to reduce the switching activities of the scan cells. It divides the unspecified bits present in the test cubes by multiples of 4 to increase the correlation between the consecutive test patterns which in turn provides better run length for test data reduction. The filled test cubes are encoded with two stage test data compression in order to reduce test data volume. In the first stage, the completely specified test sets are encoded using Alternative Statistical Run Length (ASRL) coding to enhance the test data compression. The compressed ASRL test set is encoded further using Run Length based Huffman Coding (RLHC) since ASRL codewords contain the maximum run length of oneâ;;s. Experimental results show that the proposed hybrid filling provides the scan-in average and peak-power transition reduction of 88% and 29% respectively against original test sets. The two-stage test data compression scheme achieves a maximum of 86% and an average of 76% compression ratio for ISCAS’89 benchmark circuits.

An Efficient Technique to Reduce Average and Peak Power in Scan Based BIST

Objectives: A low-transition Test Pattern Generator (TPG) known as Bit Swapping LFSR (BS-LFSR) which generates the test vectors with low transitions. This will increase the correlation and results in one transition between the consecutive test patterns. Methods: The BS-LFSR comprises of an external XOR type LFSR along with multiplexer. The bit swapped test patterns alone is not enough to reduce the average and peak power. The Weighted Transition Metric (WTM) is calculated after shifting of test patterns into the scan cells. Based on WTM values for each test pattern, scan cells are reordered to reduce the test power. Findings: The various CUTs are chosen from ISCAS 89 standard benchmark circuits. The CUTs are synthesized using RTL Compiler tool from Cadence and the scan chain inserted Gate Level Netlist are obtained for each CUT respectively. Improvements: Experimental results show that power reduction is attained by employing the technique.

Thermal Aware SOC Testing by Introducing Cooling Period

ABSTRACTPower and temperature constraint system-on-chip (SOC) testing is currently a major research topic. Because of increasing technology scaling and increase in device density of SOC, overheating is becoming a serious problem in the case of SOC testing. Most of the conventional power constrained test scheduling algorithms are unable to meet the temperature constraint. In this paper, two approaches of reducing test power and temperature of individual circuit and SOC have been presented. First approach considers reduction of leakage (which depends on previous pattern) during testing by ordering the test patterns. In the second approach, temperature aware SOC testing is considered. The cores of the SOC are tested with the ordered test patterns in a tactful way by introducing cooling time such that overall temperature of the SOC is reduced. Genetic algorithm (GA) based approach is used to minimize the total power and the temperature during testing by introducing cooling time between consecutive test patterns which are generated using ATALANTA for stuck-at fault model. Using this proposed technique, average saving of temperature is up to 91% when sufficient cooling period is introduced between consecutive test patterns.

Ring Counter Based ATPG for Low Transition Test Pattern Generation.

In test mode test patterns are applied in random fashion to the circuit under circuit. This increases switching transition between the consecutive test patterns and thereby increases dynamic power dissipation. The proposed ring counter based ATPG reduces vertical switching transitions by inserting test vectors only between the less correlative test patterns. This paper presents the RC-ATPG with an external circuit. The external circuit consists of XOR gates, full adders, and multiplexers. First the total number of transitions between the consecutive test patterns is determined. If it is more, then the external circuit generates and inserts test vectors in between the two test patterns. Test vector insertion increases the correlation between the test patterns and reduces dynamic power dissipation. The results prove that the test patterns generated by the proposed ATPG have fewer transitions than the conventional ATPG. Experimental results based on ISCAS'85 and ISCAS'89 benchmark circuits show 38.5% reduction in the average power and 50% reduction in the peak power attained during testing with a small size decoding logic.

Low Transition Test Pattern Generator Architecture for Built-in-Self-Test

Problem statement: In Built-In Self-Test (BIST), test patterns are generated and applied to the Circuit-Under-Test (CUT) by on-chip hardware; minimizing hardware overhead is a major concern of BIST implementation. In pseudorandom BIST architectures, the test patterns are generated in random nature by linear feedback shift registers. This normally requires more number of test patterns for testing the architectures which need long test time. Approach: This study presents a novel test pattern generation technique called Low-Transition Generalized Linear Feedback Shift Register (LT-GLFSR) with bipartite (half fixed) and bit insertion (either 0 or 1) techniques. Intermediate patterns (by bipartite and bit (either 0 or 1) insertion technique) inserted in between consecutive test patterns generated by GLFSR which is enabled by a non overlapping clock scheme. This process is performed by finite state machine generate sequence of control signals. Low-Transition Generalized Linear Feedback Shift Registers (LT-GLFSR), are used in a circuit under test to reduce the average and peak power during transitions. LT-GLFSR patterns high degree of randomness and correlation between consecutive patterns. LT-GLFSR does not depend on circuit under test and hence it is used for both BIST and scan-based BIST architectures. Results and Conclusion: Simulation results prove that this technique has reduction in power consumption and high fault coverage with minimum number of test patterns. The results also show that it reduces the peak and average power consumption during test for ISCAS’89 bench mark circuits.

Low Transition-Generalized Linear Feedback Shift Register Based Test Pattern Generator Architecture for Built-in-Self-Test

Problem statement: In Built-In Self-Test (BIST), test patterns are ge nerated and applied to the Circuit-Under-Test (CUT) by on-chip hardware; minimizing hardware overhead is a major concern of BIST implementation. In pseudorandom BIST architectures, the test patterns are generated in random nature by Linear Feedback Shift Registers. This nor mally requires more number of test patterns for testing the architectures which need long test time . Approach: This study presents a novel test pattern generation technique called Low-Transition Generali zed Linear Feedback Shift Register (LT-GLFSR) and it was also called Bipartite GLFSR. Intermediat e pattern (Bipartite technique) inserted in between consecutive test patterns generated by GLFSR was called LT-GLFSR technique which was enabled by a non overlapping clock scheme. Low-transition generalized linear feedback shift registers (LT-GLFSR), was used in a circuit under test to reduce the aver age and peak power during transitions. LT-GLFSR pattern generator would generate patterns with high er degree of randomness and high correlation between consecutive patterns would have efficient area impl ementation. LT-GLFSR did not depend on circuit under test and hence it could be used for both BIST and scan-based BIST architectures. Results/Conclusion: Simulation results show that this technique has re duction in power consumption and high fault coverage with minimum number of test patterns. The results also show that it reduces th e peak and average power consumption during test for ISCAS'89 bench mark circuits.

A New Scan Partition Scheme for Low-Power Embedded Systems

A new scan partition architecture to reduce both the average and peak power dissipation during scan testing is proposed for low-power embedded systems. In scan-based testing, due to the extremely high switching activity during the scan shift operation, the power consumption increases considerably. In addition, the reduced correlation between consecutive test patterns may increase the power consumed during the capture cycle. In the proposed architecture, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the spectrum of unspecified bits in the test cubes. To optimize the proposed process, a novel graph-based heuristic to partition the scan chain into several segments and a technique to increase the number of don't cares in the given test set have been developed. Experimental results on large ISCAS89 benchmark circuits show that the proposed technique, compared to the traditional full scan scheme, can reduce both the average switching activities and the average peak switching activities by 92.37% and 41.21%, respectively.

Optimal Interconnect ATPG Under a Ground-Bounce Constraint

In order to prevent ground bounce, Automatic Test Pattern Generation (ATPG) algorithms for wire interconnects have recently been extended with the capability to restrict the maximal Hamming distance between any two consecutive test patterns to a user-defined integer, referred to as the Simultaneously-Switching Outputs Limit (SSOL). The conventional approach to meet this SSOL constraint is to insert additional test patterns between consecutive test patterns if their Hamming distance is too large; this approach often leads to substantially more test patterns than strictly necessary. This paper presents an algorithm that generates, for a user-defined number of interconnect wires, a minimal set of test patterns that respects a user-defined SSOL constraint. Experimental results show that, in comparison to the conventional approach, our algorithm leads to a significant reduction of up to 60% in the test pattern count and corresponding test application time.