Abstract
In test mode test patterns are applied in random fashion to the circuit under circuit. This increases switching transition between the consecutive test patterns and thereby increases dynamic power dissipation. The proposed ring counter based ATPG reduces vertical switching transitions by inserting test vectors only between the less correlative test patterns. This paper presents the RC-ATPG with an external circuit. The external circuit consists of XOR gates, full adders, and multiplexers. First the total number of transitions between the consecutive test patterns is determined. If it is more, then the external circuit generates and inserts test vectors in between the two test patterns. Test vector insertion increases the correlation between the test patterns and reduces dynamic power dissipation. The results prove that the test patterns generated by the proposed ATPG have fewer transitions than the conventional ATPG. Experimental results based on ISCAS'85 and ISCAS'89 benchmark circuits show 38.5% reduction in the average power and 50% reduction in the peak power attained during testing with a small size decoding logic.
Highlights
Built-in self-test (BIST) is a design-for-test (DFT) technique in which testing is achieved through built-in hardware features
Power consumption during testing has become an important issue in test manufacturing because high circuit activity rate during test generation and/or high fan-out of BIST components may result in passing the package power consumption limits which in turn may risk the health of the test [1, 2]
In this paper, ring counter is used as test pattern generator and an external circuit is added with test pattern generation (TPG) for reducing switching transitions makes the circuit simple
Summary
Built-in self-test (BIST) is a design-for-test (DFT) technique in which testing is achieved through built-in hardware features. Generation of test vector sequences with low power consumption and high fault coverage in minimal hardware size is the main objective of this proposed approach. In [7, 8], low transition test vector is inserted between two consecutive patterns, even if there are a few number of transitions If number of transitions increased, test vectors are generated using random bits insertion and frozen partial test pattern. This decreases vertical transitions, reducing dynamic power dissipation.
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