Conformal Deposition Techniques Research Articles

Review—Solid and Polymer Electrolyte Materials and Related Processing Methods Suitable for Three-Dimensional Battery Architectures

Three-dimensional (3D) battery architectures have been envisioned to enable high energy density electrodes without the associated power drop experienced by planar cells. However, the development of 3D cells is hampered by difficulties producing conformal solid-state electrolytes (SSE), solid polymer electrolytes (SPE) and gel polymer electrolytes (GPE) that are pinhole-free and have adequate ionic conductivities. Fortunately, electrolytes in 3D cells are often utilized at lower thickness, which may compensate the decreased ionic conductivity. Here, we comprehensively review potential 3D SSE, SPE and GPE electrolyte materials by compiling their thickness and room temperature ionic conductivity. We use area specific resistance (ASR) as a metric to compare 3D electrolytes with one another and conventional electrolytes. We find that certain process-material combinations, such as atomic layer deposition of SSEs, electrodeposition of SPEs and GPEs, and initiated chemical vapor deposition of SPEs demonstrate ASRs beneath the interfacial impedances of Li-based systems and approach state-of-the-art electrolytes. We also comment on additional factors, such as electrochemical stability, that should be evaluated when determining 3D electrolyte suitability. Future research should focus on adapting known materials chemistries for conformal deposition techniques to further improve the ionic conductivity, as these techniques are capable of producing the necessary thicknesses and conformality.

(Keynote) ALD Challenges and Opportunities in Light of Future Trends in Si-Based Nanoelectronics

To enable CMOS transistor density scaling following Moore’s Law, device architectures transitioned in the past decade from the historical 2D planar transistor to FINFET. The next innovation touted for the 3nm node is a 3D stacked gate-all-around architecture in combination with a backside power delivery network. For further scaling, stacking nmos and pmos, the so-called complementary-FET (CFET) design, is envisaged to happen in 2030. The shrinking device dimensions of the interconnects require also new metallization schemes to tackle the RC challenge, such as Cu replacements materials in a direct metal etch integration scheme. Beyond the CFET era, one envisages the introduction of 2D-grown channel materials that will pave the way for further scaling. A broad variety of complementary deposition techniques will be needed to enable the above-mentioned novelties; among them ALD that will play a crucial role.A similar trend towards stacking functional cells can be observed in various memories, such as the emerging memories that aim to bridge the gap between DRAM and NAND, thereby enabling fast data storage and retreival for real-time processing in connected devices at low cost. These memories are based on phase change, filamentary, magnetic, or ferroelectric mechanisms and often use multi-element materials. They have been extensively explored in 2D capacitor or transistor based devices, but for further density scaling 3D device designs are needed where a conformal deposition technique such as ALD is required. Cell scaling challenges also hold for the traditional DRAM which lead to exploring 3DDRAM integration routes. One viable pathway for scaling implies the replacement of the typical Si-channel based transistor by a deposited semiconductor oxide channel. Ultimate 3DDRAM implementation would require a conformal deposition of that channel.In this presentation, we will discuss the opportunities and challenges of ALD in a 3D-evolving device landscape where new materials will play a key role.

300 mm integration of a scalable phase change material spacer by inductively coupled plasma etching

To improve the heating efficiency and reduce the reset current of phase change memory, the volume-confined cells have been widely studied by employing highly conformal deposition techniques. In this work, a scalable confined structure with sidewall phase change material spacer is investigated for the integration in 12-inch wafer using physical vapor deposition and the subsequent anisotropic plasma etching back process. The finite element simulations reveal a remarkable 80% increase in heating efficiency by taking the confined structure. The isolated and compact trenches with the aspect ratio ranging from 0.40 to 1.04 are designed to accommodate the sidewall phase change material. The scaling down of the critical dimension of the rail-like spacer is observed as the aspect ratio increases. The spacer width of around 34 nm is well beyond the lithography capability used in this study. These results provide a promising path to fabricate the low-power and high-density memory device in a way fully compatible with the manufacturing technology.

Atomic layer deposition of germanium-selenium-tellurium compounds for low-leakage, tunable ovonic threshold switches

Chalcogenide compounds are leading a revolution in the electronic memories space. Phase-change-memory (PCM) elements and ovonic threshold switches (OTSs) combined in the cross-point (X-point) architecture produce memory arrays with access and write times orders of magnitude faster than state-of-the-art flash nands and also provide nonvolatile storage, a larger scale of integration compared to traditional memory arrays, and the opportunity to develop beyond von Neumann architectures to support computationally demanding applications such as artificial intelligence. The commercial success of chalcogenide X-point arrays will depend on the ability to integrate chalcogenide films into sophisticated three-dimensional architectures such as vertical structures for economical manufacturing. To do so, highly conformal deposition techniques are required such as atomic layer deposition (ALD). State-of-the-art chalcogenide cross-point devices are currently fabricated using PVD, which fails to provide any film conformality. ALD PCMs with performance comparable to their PVD counterparts have been demonstrated; however, fabricating OTS selectors using ALD remains a challenge. Here, we present an approach to deposit ALD ternary germanium-selenium-tellurium (Ge-Se-Te) spanning a wide range of compositions. The ALD Ge-Se-Te films show excellent conformality, low surface roughness, and good compositional homogeneity. We fabricated OTS devices and demonstrated the ability to produce low leakage selectors with threshold voltage tuning achieved by control over the film composition.

Deposition of Conformal Catalyst Coatings on Porous Electrodes Using a Layer-By-Layer Surface Sol-Gel Process

The state-of-the-art cathode of solid oxide fuel cells suffers from accelerated degradation and slow reaction kinetics for the oxygen reduction reaction (ORR). Surface modification of the cathode has been widely investigated and shown to greatly improve catalytic activity and prevent the formation of insulating phases. However, there is a need to improve the quality of the surface modification coatings while reducing the cost. In this presentation, we report a novel surface modification technique, coined layer-by-layer surface sol-gel (LbL SSG), for deposition of BaO and Pr2O3 on a porous La0.6Sr0.4Co0.2Fe0.8O3-δ (LSCF) cathode, greatly increasing the catalytic activity for ORR and tolerance against contaminants. This low-cost, liquid phase deposition technique produces conformal coatings with precise thickness control by utilizing alternating self-limiting reactions between chemisorbed metal alkoxides and water on hydroxyl-rich surfaces. The availability of many different metal alkoxide precursors previously proved in traditional sol-gel processes, capability to deposit at room temperature, and lack of expensive vacuum equipment make this technique extremely promising over other conformal deposition techniques such as atomic layer deposition. LbL SSG is shown to produce much more conformal coatings throughout the entire porous cathode and further reduce degradation over similar coatings produced via solution infiltration. Electrochemical impedance spectroscopy analysis shows a great reduction in polarization resistance of symmetrical cells with electrodes modified by catalyst coatings. Utilizing the precise thickness control of the layer by layer process via deposition cycle count, the optimum thickness is determined to be about 8 nm (derived from 30 cycles). Thinner films are shown to be instable, breaking down and degrading over the first 30 hours, while thicker films increase the polarization resistance due to the lower ionic conductivity of the catalyst coatings. The process also demonstrates excellent scalability and versatility by coating larger cathodes (one inch in diameter) and depositing various oxides using different metal alkoxide precursors. Figure 1. SEM images of bare and coated porous electrodes showing the conformal BaO film deposited via LbL SSG. The polarization resistance versus time for various deposition cycle counts showing greatly improved stability for coated cells. Figure 1

Toward 3D Thin-Film Batteries: Optimal Current-Collector Design and Scalable Fabrication of TiO2 Thin-Film Electrodes

Three-dimensional (3D) thin-film solid-state batteries are an interesting concept for microstorage, promising high footprint capacity, fast charging, safety, and long lifetime. However, to realize their commercialization, several challenges still need to be overcome. In this work, we focus on two issues: the conformal coating and the high throughput deposition of thin-film layers. First, to facilitate conformal deposition, a design based on 3D micropillars is chosen. Although such a design has been suggested in the past, we calculate for the first time what (footprint) capacities can be expected when using fully optimized pillar geometries while taking practical manufacturability into consideration. Next, spatial atomic layer deposition (S-ALD) is investigated as a scalable and conformal deposition technique. As proof-of-concept, 100 nm Cl-doped am-TiO2 thin-film electrodes are deposited by S-ALD on TiN-coated silicon micropillars. The influence of deposition parameters (i.e., exposure time and temperature) on the conformality and uniformity across the micropillar substrate is investigated. The results are discussed in terms of precursor diffusion and depletion, which is supported by an analytical model developed for our micropillar array. Furthermore, the Li-ion insertion properties of 3D electrodes fabricated by S-ALD and conventional ALD are compared. This research highlights the challenges and promises of 3D microbatteries and guides future S-ALD development to enable conformal and high-throughput thin-film deposition.

Conformal Vanadium Oxides Beyond Crystalline V2O5 As High Energy Density 3D Thin-Film Electrodes for Lithium-Ion Batteries

The nearly unmatched conformality of Atomic Layer Deposition (ALD) renders it a powerful deposition technique for applications such as catalysis where high surface areas are critical, or for protective coatings on complex 3D surfaces such as powders or porous materials. In the last decade, ALD for energy storage has come into view. Advances in technology have pushed the requirements of energy storage devices, leading to novel lithium-ion battery (LIB) concepts such as 3D-structured electrodes, thin-film electrode and the combination of both. These concepts enable high-power and high-energy integrateable batteries, but require a conformal deposition technique for the current collectors, electrodes, solid electrolytes and interfacial coatings alike. Besides 3D structuring, materials design of the LIB electrodes is paramount to achieve higher power and higher energy densities, beyond traditional electrode materials such as LiCoO2, and LiMnO2which are limited to volumetric capacities of 550-700mAh/cm³. Traditionally, the main focus of materials development for batteries has been on crystalline compounds. However, several indications exist that higher energy and power density can be found in amorphous materials. ALD is not only excellently suited to deposit conformal films, but also able to grow high-quality amorphous films at low deposition temperatures, enabling the study of amorphous thin-film electrodes. In this work, ALD of vanadium oxides for applications as lithium-ion electrodes is envisioned. Vanadium oxides were amongst the first materials to be studied as LIB cathodes, but were never commercialised. V2O5 is a well-known LIB electrode, but the rather low volumetric energy density (when storing one lithium) or poor cyclability (when storing 2-3 lithium ions) have prevented its large-scale commercialisation in the past. Here, we demonstrate the ALD deposition of amorphous and crystalline V2O5, and two ‘flavours’ of amorphous VO2, from a single vanadium precursor (Tetrakis[ethylmethylamino] vanadium). We demonstrate the crystallisation of these films into crystalline films in the Wadsley series, and are able to unravel the influence of initial ALD process, atmosphere, temperature and substrate on the crystallization and oxidation of the VO2 films. With this in mind, we are able to obtain phase-pure crystalline vanadium oxides in the whole Wadsley series (VO2–V6O13–V4O9–V3O7–V2O5), which show very high energy densities up to more than double that of typical bulk cathodes (1380mAh/cm³ for V4O9). The amorphous initial states (amorphous VO2 and V2O5) are often not considered due to their lack of a clearly defined electrode potential. However, building on the nature of ALD to grow high-purity amorphous films, these were also investigated here. It was found that, besides also having very high capacities, their kinetics are excellent. Finally, the best candidates were examined on an ALD Pt-coated silicon micropillar array as 3D-structured thin-film electrodes. The 20x surface enhancement of the micropillar substrate enhanced the footprint capacity of the 40nm films from approximately 2-5µAh/cm² to 40-100µAh/cm², with the highest capacity for amorphous VO2(>100µAh/cm² for the 40nm film), while at the same time maintaining the excellent thin-film kinetics of the planar films, in effect simultaneously demonstrating the potential of ALD to deposit 3D thin-film electrodes as well as a tool to study amorphous and crystalline films. In conclusion, a wide range of crystalline and amorphous vanadium oxides were demonstrated from a single vanadium-precursor based ALD process. All films were examined as potential lithium-ion battery electrodes, and showed promise of very high volumetric capacities. In particular, the amorphous films and the crystalline VO2 (B) not only displayed very high capacities, but also excellent kinetics, enabling both high-energy and high-power electrodes. Figure 1

High aspect ratio and low leakage current carbon nanosheets based high-k nanostructure for energy storage applications

Carbon nanosheets (CNS) are exploited to fabricate a high aspect ratio strontium titanate (STO) structure with very low leakage current density. CNS are grown by chemical vapor deposition (CVD) on 70nm layer of TiN coated Si wafers. Atomic layer deposition (ALD) is employed as a conformal deposition technique for Sr-rich STO on top of 3D CNS to obtain a conformal STO layer with high area per footprint. The area enhancement resulting from CNS is investigated using electrochemical impedance spectroscopy (EIS) for conformally deposited Al2O3 thin films based TIN blanket and CNS, electrodes. It is investigated by comparing the capacitance enhancement resulted from CNS/Al2O3 capacitors with that obtained from blanket TiN/ Al2O3 capacitors. Our findings show that EIS is very promising for estimating the area increase for different nanostructures. The electrochemical spectroscopy show typical capacitor behavior for CNS based electrochemical capacitors. Moreover, solid-state electrical characterizations for CNS/STO based metal-insulator-metal (MIM) capacitors show very low leakage current density with strong breakdown and excellent area scaling through the potential window [0V, +10V].

3D Structuring of Thin Film Solid State Li-Ion Cells for Fast Charging Micro-Batteries

High energy and power density are the main requirements of today’s high demanding applications in consumer electronics. Lithium ion batteries (LIB) have the highest energy density of all known systems and are thus the best choice for rechargeable micro-batteries. Liquid electrolyte LIBs present limitations in safety, size and design, where all-solid state thin film batteries are considered to overcome these restrictions for small devices. Although planar all-solid state thin film LIBs are at present commercially available, they provide low capacity (<1mAh/cm2) which limits their application scenario. By using micro-structured surfaces (i.e. 3D batteries) and appropriate conformal coating technologies (i.e. electrochemical deposition, ALD), the capacity can be increased while still keeping a high rate performance. The main challenges in the introduction of solid-state LIBs are low ionic conductance and limited cycle life time due to mechanical stress and shearing interfaces. Novel materials and innovative nanostructures have to be explored in order to overcome these limitations. Thin film 3D compatible materials need to provide with the necessary requirements for functional and viable thin-film stacks. Thin film electrodes offer shorter Li-diffusion paths which allow them to be used at ultra-fast charging rates while keeping their maximum capacities. Thin film electrolytes with intrinsically high ion conductivity (~10-3 S/cm) do exist, but are not electrochemically stable. On the other hand, electronically insulating electrolytes with a large electrochemical window and good chemical stability are known, but typically have intrinsically low ionic conductivities (<10-6S/cm). In addition, there is the need for conformal deposition techniques which can offer pinhole-free coverage over large surface areas with large aspect ratio features for electrode, electrolyte and buffer layers. In this paper, we present the fabrication of 3D thin-film batteries using high aspect ratio silicon pillar arrays providing area enhancement of over 25x. The pillars are conformally coated with LiMn2O4 (LMO) and LixTiO2 as positive and negative electrodes, respectively. For the electrolyte, thin-film composite electrolyte films are being developed. Where we currently focus on 60 μm high pillars with a 2 μm diameter and pitch, the energy and power output per unit area of the battery can be increased by scaling towards higher aspect ratio pillars. Indeed, by increasing the height of the pillars, more active material per unit area can be deposited, resulting in a higher capacity. Simultaneously, the power output of the battery improves due to the increased internal surface of the 3D battery. Notice that a similar approach is not possible with conventional thin-film batteries. Increasing the active film thickness in these batteries results in more capacity, but this goes at the cost of power output due to the increased resistance of the thicker active layers. In addition, by decreasing the pitch between the pillars, the film thickness can be scaled down. We show that the available capacity of both the manganate and titania based films can be increased by scaling down the film thickness below 100 nm without affecting cycle life time. The thinnest films show the highest volumetric capacity and the best cycling stability. The increased stability of the LMO films below 50 nm allows cycling in both the 4 and 3V potential region, resulting in a high volumetric capacity of 1.2Ah/cm3. The potential of 3D thin-film batteries with respect to attainable energy density and C-rate performance will be discussed. Figure 1

(Invited) Engineered Combinations of Inorganic ALD/CVD Layers and Monomolecular Organic Films

Capacitance scaling in damascene interconnects is achieved by introducing ultra-porous low dielectric constant materials. Nevertheless, one of the key issues in the integration of such porous materials is their inability to prevent gaseous penetration, e.g. during the metallization. Several strategies are being followed to minimize the processing damage to the porous films during etching and ashing. The subsequent important step is to seal the pores at the surface, especially at the sidewalls after the trench and via etching. This is to prevent metal or precursor penetration during the metallization process, especially by advanced conformal deposition techniques such as chemical vapor deposition (CVD) and atomic layer deposition (ALD). There are several routes to sealing: i) by thin film deposition; ii) by plasma-surface interaction; iii) by surface cross-linking/reconstruction. In this contribution, we report about the achievement of a complete pore sealing by combining a surface treatment of the low-k material together with self-assembled monolayers (SAMs) deposition and a low temperature ALD and CVD processes. In particular, CVD-based MnSixOy films are serious candidates for sub-25 nm-wide trench and via metallization technology because of their conformal nature and their ability to act as effective Cu diffusion barriers in the range of 1-2 nm thickness. Self-assembled molecular nanolayers composed of sub-1 nm organic chains and terminated with desired functional groups are attractive for modifying surface properties for a variety of applications, such as lubricants, in nanolithography, corrosion protection and in the crystallization of biominerals. Monolayers can help engineering thin-film interfaces, both as active components in molecular devices, and as passive layers, inhibiting interfacial diffusion, promoting adhesion and toughening brittle nanoporous structures. In this contribution, we report about the interaction between CVD and ALD films and organic thin films. Special attention is paid to selective ALD/CVD growth on functionalized surfaces having modulated surface energies.

Spatial Atmospheric ALD of Functional Layers for CIGS Solar Cells

Copper Indium Gallium di-Selenide (CIGS) solar cells are a promising approach in photovoltaic technology, having low production costs, high conversion efficiencies (> 20 %), as well as the possibility to manufacture them on flexible substrates. State-of-the-art in CIGS solar cells manufacturing is to use a stack of CdS, intrinsic ZnO (i-ZnO) and an Al-doped ZnO TCO on top of the CIGS film. Replacement of CdS by a non-toxic Cd-free layer with wider band gap (> 2.4 eV) would a) decrease the production cost by avoiding the expensive treatment of toxic wastes and b) increase the overall cell efficiency by enhancing the quantum efficiency in the blue range. Moreover, the use of a “soft” and highly conformal deposition technique is preferred to improve the electrical properties of the buffer layer/CIGS interface. In this paper we present spatial atmospheric atomic layer deposition of a Zn(O,S) buffer layer as CdS replacement for CIGS solar cells. Spatial ALD is emerging as an industrially scalable deposition technique at atmospheric pressure which combines the advantages of temporal ALD, i.e. excellent control of film composition and uniformity on large area substrates, with high growth rates (up to nm/s). Films are grown by sequentially exposing the substrate to oxygen and sulfur precursors (H2O, H2S) and the zinc metal precursor (i.e., DEZn). By controlling the kinetics of surface reactions between evaporated precursors and reactive sites at the film surface, the composition of Zn(O,S) can be precisely tuned. The incorporation of S into ZnO results in a bowing of the band gap in the range from 3.3 eV (ZnO) to 2.7 (S/O+S ~ 0.5) and 3.4 eV (ZnS), as measured by spectrophotometry. The morphology of the Zn(Ox-1,Sx) films varies from polycrystalline (for 0<x<30 and 70<x<100) to amorphous (30<x<70), as measured by X-ray diffraction. CIGS solar cells with a Zn(O,S) buffer layer show an increased spectral response around 400 nm compared to solar cells with a CdS buffer layer. The solar cells with the Zn(O,S) buffer layer had an efficiency of 15.9 %, compared to 15.5 % for the reference solar cells with a CdS buffer layer.

Conformal Electrodeposition for All-Solid-State 3D Thin-Film Batteries

For the application of durable micro-storage for autonomous systems and implants, 3D thin-film batteries are leading candidates. Lithium ion batteries have the highest energy density of all known systems and are thus the best choice for these rechargeable micro-batteries. Since liquid electrolyte based batteries present safety issues and limitations in size and design, pure solid state devices are considered particularly for miniaturization. Planar thin-film lithium and lithium ion batteries are at present commercially available but have limited capacity (<1mAh/cm2). The capacity can be increased by coating the thin-film stacks on micro-or nanostructured surfaces (3D thin-film batteries, see Figure below). The increase in surface area through 3D structuring also increases the maximum current and thus the battery power. The main challenges in the introduction of solid-state Li-ion batteries are low ionic conductance and limited cycle life time due to mechanical stress and shearing interfaces. Solid materials with intrinsically high ion conductivity (~10-3 S.cm) do exist, but are not electrochemically stable. Vice versa, electronically insulating electrolytes with a large electrochemical window and good chemical stability to metallic Li are known, but typically have intrinsically low ionic conductivities (<10-6 S cm). By scaling down the electrolyte thickness, an overall acceptable ionic conductivity can be obtained even for material with poor ionic conductivity. The latter assumes conformal and pinhole-free coverage over large effective surface areas with large aspect ratio features. ALD is a surface sensitive technique that can provide superior conformal coatings of high-aspect ratio features, crevices and corners and is suitable for (but not limited to) ultra-thin films. In this paper, the requirements for functional and viable thin-film stacks will be discussed. The need for conformal deposition techniques such as ECD, ALD and MLD for electrode, electrolyte and buffer layers will be addressed. The mechanical integrity of the all-solid state stack in corners and confined spaces is a tangible issue. Considerable mechanical stress may build up during charge and discharge due to the rigid nature of the inorganic crystals and glasses that make up the battery stack. Furthermore, in-diffusion of at interfaces may consume part of the electrode which next to capacity and power loss can affect device reliability. In this paper, the importance of thin buffer layers will be discoursed. Part of the current collector/anode/electrolyte/cathode/current collector can be made by electrochemical deposition. Electronically resistive materials such as oxides and dielectric polymers can be electrodeposited with extreme conformality as a result of the self-limiting kinetics. In this paper we will show the electrodeposition of MnO2 as potential positive Li-ion electrode and the electro-polymerization of poly phenylene oxide (PPO) as two examples were ECD can built part the battery stack on micro-structured surfaces with great potential for cost-effective up scaling to large area foil-based processing.

(Invited) All-Solid-State Batteries: A Challenging Route towards 3D Integration

Current trends in device miniaturization and portability put strong requirements on energy storage devices with a high power to volume ratio. Li-ion all-solid-state batteries are very attractive as they combine a high storage capacity with the possibility of a flexible design and a longer lifespan than comparable battery technologies. As these storage devices approach the nano-scale, thin film conformal deposition techniques (such as PVD, (LP)CVD and ALD) become increasingly important. In this paper an outlook is given on the challenging route towards 3D integrated all-solid-state batteries and materials are suggested and discussed for each individual layer of a battery stack.

Atomic Layer Deposition for All-Solid-State 3D-Integrated Batteries

All-solid-state 3D integrated batteries can reach the energy storage capacity required for future wireless devices by exploiting the third dimension. Conformal deposition techniques such as atomic layer deposition (ALD) are needed to deposit the battery materials. In this work, the current development of ALD processes for 3D integrated batteries is reviewed. We have developed both the TiN diffusion barrier and Pt cathode current collector processes. TiN showed good barrier properties in 3D, although a higher than expected charge density was observed, which could be attributed to a lower thickness and/or different material properties at the bottom of the 3D structures. The remote plasma ALD process for Pt showed fast growth initiation and good adhesion of the films. Furthermore, sufficient step coverage for the battery application was found. ALD is also potentially able to deposit the active battery layers, although the deposition of Li-containing materials is expected to be challenging.

High-k Dielectrics and Metal Gates for Future Generation Memory Devices

The requirements and development of high-k dielectric films for application in storage cells of future generation flash and Dynamic Random Access Memory (DRAM) devices are reviewed. Dielectrics with k-value in the 9-30 range are studied as insulators between charge storage layers and control gates in flash devices. For this application, large band gaps (> 6 eV) and band offsets are required, as well as low trap densities. Materials studied include aluminates and scandates. For DRAM metal-insulator-metal (MIM) capacitors, aggressive scaling of the equivalent oxide thickness (with targets down to 0.3 nm) drives the research towards dielectrics with k-values > 50. Due to the high aspect ratio of MIMCap structures, highly conformal deposition techniques are needed, triggering a substantial effort to develop Atomic Layer Deposition (ALD) processes for the deposition of metal gates and high-k dielectrics. Materials studied include Sr and Ba-based perovskites, with SrTiO3 as one of the most promising candidates, as well as tantalates, titanates and niobates.

High- k dielectrics for future generation memory devices (Invited Paper)

The requirements and development of high- k dielectric films for application in storage cells of future generation flash and Dynamic Random Access Memory (DRAM) devices are reviewed. Dielectrics with k-value in the 9–30 range are studied as insulators between charge storage layers and control gates in flash devices. For this application, large band gaps (>6 eV) and band offsets are required, as well as low trap densities. Materials studied include aluminates and scandates. For DRAM metal–insulator–metal (MIM) capacitors, aggressive scaling of the equivalent oxide thickness (with targets down to 0.3 nm) drives the research towards dielectrics with k-values >50. Due to the high aspect ratio of MIMCap structures, highly conformal deposition techniques are needed, triggering a substantial effort to develop Atomic Layer Deposition (ALD) processes for the deposition of metal gates and high- k dielectrics. Materials studied include Sr- and Ba-based perovskites, with SrTiO 3 as one of the most promising candidates, as well as tantalates, titanates and niobates.

Chemical vapor deposition of (Ba,Sr)TiO3 thin films for application in gigabit scale dynamic random access memories

Our recent study respecting chemical vapor deposition of (Ba, Sr)TiO3 thin films was discussed focusing on conformal deposition technique and composition control. Perfect conformal (Ba, Sr)TiO3 films were deposited under the kinetically limited condition using Ba(THD)2-Sr(THD)2-TiO(THD)2 (THD is 2,2,6,6-tetramethyl-3,5-heptanedione) source system. We successfully fabricated three-dimensional capacitors using this conformal deposition technique. Under the kinetically limited condition, the Ba/Sr composition ratio was determined by the partial pressure ratio of Ba(THD)2 and Sr(THD)2. The self-matching of Ti/(Ba+Sr) stoichiometry occurred under a certain TiO(THD)2 supply range. It was proposed that the possible important reactant species were (THD)2Ba-O-Ti(THD)2 and (THD)2Sr-O-Ti(THD)2 dimers.