Configuration RAM Research Articles

Proton irradiation of FPGA-embedded hadron fluence sensors

Hadron fluence monitors based on static random access memories (SRAMs) are in use at particle accelerators for the protection of electronics and at proton-therapy facilities for measuring secondary neutrons. One shortcoming of current solutions is that they necessitate SRAMs to detect radiation-induced single event upsets and require additional components to transfer the counts from the radiation area. This approach limits the practicality of the sensors due to their power requirements, increased board complexity, larger physical footprint and reduced total ionizing dose tolerance. In this work, we present proton irradiation test results of a novel proton and neutron fluence sensor we designed. The sensor is fully embedded in a SRAM-based field programmable gate array (FPGA) solving the abovementioned limitations of the state of the art. The FPGA configuration SRAM is used as a sensitive element, while the Joint Test Action Group interface is leveraged as a read out circuitry. We irradiated six sensor units by means of a variable-energy proton beam at the Trento Institute for Fundamental Physics and Applications (TIFPA, Trento, Italy). We discuss our results in terms of proton to upset cross section as a function of the proton energy in the range from 70 to 228 MeV, also parameterized with respect to the power supply voltage. We evaluate the variability of the cross section in the set of irradiated samples. Moreover, we show how we used the device to image the proton beam and measure beam profiles for aligning the configuration RAM and beam centers. We also suggest alternate reading modes to measure the fluence on the device by measuring the drawn current, rather than counting upsets.

Evaluation of SEU impact on convolutional neural networks based on BRAM and CRAM in FPGAs

This study evaluates the sensitivity of FPGA-based CNN systems and the efficacy of selective hardening approaches with laser injection and proton irradiation. The LeNet-5 CNN architecture was taken as a case study. First, the entire CNN with block random access memory (BRAM) attached is evaluated by laser test scanning, and errors generated from each layer are detected to determine the most critical layer. Second, the same network is evaluated without BRAM, considering only the configuration RAM (CRAM) and errors generated from each layer are detected. Third, the impact of laser scan errors from BRAM and CRAM are compared, while tracing the layers in which these errors are generated. Then, proton testing is performed on the entire CNN, and errors from each layer are detected and compared to validate the laser scanning test. Experimental results from laser and proton demonstrate that CRAM errors have a larger impact on CNN layers than BRAM errors. Regarding layer criticality, the second convolutional layer (C2) appears to be the most critical one because it generates most CRAM errors. This was validated by serial and parallel designs, where both confirm similar trends. Accordingly, the partial triple modular redundancy (TMR) approach is only applied to the critical portions, leading to around 40 % reliability improvement with less than 20 % overhead.

SEE sensitivity of a COTS 28-nm SRAM-based FPGA under thermal neutrons and different incident angles

This paper provides an experimental study of the single-event upset (SEU) susceptibility against thermal neutron radiation of a 28-nm bulk Commercial-Off-The-Shelf (COTS) Xilinx Artix-7 FPGA under different angles of incidence. Experimental results indicating SEUs on configuration RAM (CRAM) cells, Flip-Flops (FFs), and Block RAMs (BRAMs) are presented and discussed. Shapes of multiple events (ranging from 2 to 12-bit) are also analyzed, and their dependency on the incident angle of the particle beam against the device's surface. Possible shapes of 128 and 384-bit multiple events are also investigated, revealing a trend to follow word lines. The results of the front incident angle are compared with 14.2-MeV neutrons, demonstrating a considerable difference in the device's sensitivity against both irradiation sources. Finally, a modeling tool called MUSCA-SEP3 is used to predict the device's sensitivity under the same environmental conditions. The obtained experimental results will show a good agreement with the predicted ones in a very accurate way.

Neutron-induced single event effect in Xilinx 16nm MPSoC configuration RAM (CRAM) using white neutron and 2.72~81.8meV neutron in CSNS-BL20

ABSTRACT Multi-Processor System on Chip is widely used in 5G wireless, advanced driver assistance system, industrial internet of things and other fields, it suffers the risk from neutron-induced single event effects. In the China Spallation Neutron Source BL20 neutron performance measurement room, the white and 2.72~81.8meV neutrons are obtained by adjusting the phase of the choppers, and the neutron-induced single event effect experiments on configuration memory of the Xilinx 16nm MPSoC were carried out. Single bit upset and single event functional interruption events were detected in various irradiation modes. The results show that 16nm MPSoC is sensitive to low energy neutrons because of 10B. Analysis shows that 2.72~81.8meV neutrons take up about 7.1% of the white neutron, but the contribution to the entire white neutron inducing single event upsets reaches 63%. Further analysis manifests that neutrons in the thermal energy region account for about 9.6% in white neutron irradiation mode, but their contribution to single event upset is about 44%. And for 2.72~81.8meV neutron irradiation mode, neutrons from 2.72 to 10meV and 10 to 81.8meV contributed 46% and 54% of soft errors, respectively. Therefore, for certain radiation fields, it is recommended to focus on the impact of low energy neutrons.

Identifying Radiation-Induced Micro-SEFIs in SRAM FPGAs

Field-programmable gate arrays (FPGAs) are susceptible to radiation-induced effects that can affect more than one memory cell. Radiation-induced microsingle event functional interrupts (micro-SEFIs) are one of such events that can upset several bits at a time. These events need to be studied because they can overcome protection from techniques such as triple modular redundancy (TMR) and error correction codes (ECCs). Extracting these events from radiation data helps to understand if specific resources of the FPGA are more vulnerable and the extent of this vulnerability. This article presents a method based on statistics and fault injection to identify micro-SEFIs from beam-test data in the configuration memory and block RAM (BRAM) of SRAM-based FPGAs. The results show the cross section of these events for the configuration RAM (CRAM) and BRAM for three families of Xilinx SRAM FPGAs gathered throughout three neutron tests. This article also contains data from a fault injection campaign to uncover the possible CRAM source bits causing micro-SEFIs in memory look-up tables (LUTs) of Xilinx 7-series and Ultrascale devices.

Radiation Tolerance of Online Trigger System for COMET Phase-I

The COMET experiment aims to search for the neutrinoless muon to electron transition process with new sensitivity levels. The online trigger system is an integral part of achieving the sensitivity levels required and will be subject to an expected neutron fluence of up to $10^{12}$ $n \cdot \mathrm{cm}^{-2}\;$ within regions inside the detector solenoid. Consequently a significant number of soft errors in the logic of the onboard field programmable gate arrays (FPGA) can occur, requiring error correction for single event upsets and firmware reprogramming schemes for unrecoverable soft errors. We studied the radiation tolerance of the COMET Phase-I front-end trigger system, called COTTRI, subject to neutron fluence on order $10^{12}$ $n \cdot \mathrm{cm}^{-2}\;$ with multiple error correcting codes and automatic firmware reconfiguration. The regions measured were the configuration RAM, block RAM and also in a multi-gigabit transfer link using copper cables that will be used for communication between different trigger boards during Phase-I. The resulting cross sections observed suggest the most significant impact to the experiment will come from unrecoverable soft errors in configuration RAM, with dead time expected to be $(4.2 \pm 1.3)\%$. The effect of multi-bit errors in block RAM was found to be almost negligible in COMET Phase-I. In addition, multiple solutions have already been proposed in order to suppress these errors further. Soft errors observed in the multi-gigabit transfer links were measured to be of two orders of magnitude less impact compared to the unrecoverable errors in configuration RAM. We concluded that the COTTRI system meets the trigger requirement in COMET Phase-I.

Single Event Upsets Under 14-MeV Neutrons in a 28-nm SRAM-Based FPGA in Static Mode

A sensitivity characterization of a Xilinx Artix-7 field programmable gate array (FPGA) against 14.2-MeV neutrons is presented. The content of the internal static random access memories (SRAMs) and flip-flops was downloaded in a PC and compared with a golden version of it. Flipped cells were identified and classified as cells of the configuration RAM, block RAM (BRAM), or flip-flops. Single bit upsets (SBUs) and multiple cell upsets (MCUs) with multiplicities ranging from 2 to 8 were identified using a statistical method. Possible shapes of multiple events are also investigated, showing a trend to follow wordlines. Finally, MUlti-Scales Single Event Phenomena Predictive Platform (MUSCA SEP3) was used to make assessment of actual environments and an improvement of single event upset (SEU) injection test is proposed.

Research on fault injection system of FPGA in irradiation environment

This article studied the frame structure of Xilinx FPGA configuration RAM, giving the method of extracting the frame structure and providing the order of frames in the bit stream file. The structure of the intermediate file of SEM IP core is also analyzed to get the positions of essential bits. Performing 0/1 flipping on the essential bits is a way to simulate the single event upset which the circuit is sensitive to under the radiation environment. A PC-side interface is designed to implement a human-machine interaction. The fault injection system is implemented on the FPGA chip, and the read and write of configuration RAM data are realized through ICAP without the need of the processor. The operation of flipping and repairing test classifies essential bits into some categories. The classification results can be used to protect the key bits in subsequent fault repairing.

Space radiation impact on smallsats during maximum and minimum solar activity

The trend towards the development of small satellites, or smallsats, has been increasing over the last few years. However, the harsh space radiation environment in which these smallsats operate provides a challenge to their survivability as their desired mission lengths increase from a few months to several years also. Smallsats typically use commercial off the shelf components (COTS) that are built for ground operations, not space use. Therefore, they may be more susceptible to the hazards of space radiation than traditional spacecraft which are typically designed to withstand the high radiation levels of space. The present paper provides a targeted assessment of representative COTS components using up to date models of the space radiation environment and its effects on smallsats in a polar Low Earth Orbit (LEO). This orbit will be assumed to be sun synchronous (98.5° inclination) and at an altitude of 800 km. We employed the new Solar Accumulated and Peak Proton and Heavy Ion Radiation Environment (SAPPHIRE) model which has been released recently in 2018, ISO-15390 GCR model, and AP8/AE8 models to estimate the space radiation environment for solar particles, galactic cosmic rays (GCRs), and trapped protons and electrons respectively. The basic damage effects that can be produced in materials and electronics in this orbit due to their exposure to the space radiation are evaluated. These effects are the Total Ionizing Dose (TID), Displacement Damage Dose (DDD), and Single Event Effects (SEE) as represented by Single Event Upsets (SEUs). SEU is evaluated for different COTS components which are believed to be representative of an optimum blend of capability and cost-effectiveness for the next generation of smallsats, including 20 nm Xilinx Kintex Ultra Scale FPGA Configuration RAM (XCKU040), 90-nm SRAM, and MLC NAND flash memory (MT29F128G08CBECBH6). For comparative purposes, the analyses are performed for both maximum and minimum solar activity.Based on these comparisons, we find as expected that the space radiation environment parameters vary with solar activity. The fluence of trapped electrons and solar protons at solar maximum are higher than those at solar minimum in contrast to the trapped protons and galactic cosmic rays at low altitudes. On the other hand, TID, DDD, and SEE all show higher values during maximum solar activity than during minimum solar activity.The use of shielding material for small satellites is mandatory for this orbit as observed TID, DDD, and SEES levels that can be reached are potentially of concern to designers. However, using Al shielding thickness of at least 1.5 mm can reduce the radiation effects to acceptable levels, for both maximum and minimum solar activity for missions of moderate (∼3 years) duration.

Soft Errors Induced by High-Energy Electrons

In the semiconductor reliability community, soft error research has primarily focused on neutrons and alpha particles. However, there are certain situations and environments in which high-energy electrons may also lead to soft errors. In this paper, we show that high energy electrons and the secondary particles created by them are capable of producing soft errors. In this paper, the energy dependence of electron-induced soft errors in a 28 nm bulk CMOS SRAM-based FPGA is recorded. Error rates are measured in both the embedded RAM and configuration RAM of the FPGA. This paper is the first research to explore the energy dependence of electron-induced single-event upsets in a commercial-off-the-shelf device. The measured electron-induced error cross sections are between $10^{{-20}}$ and $10^{{-17}}~ {\rm cm}^{{2}}$ /bit depending on memory cell tested and the electron energy. Monte Carlo energy deposition simulations are used to further explore the mechanisms involved.

Floorplanning for High Utilization of Heterogeneous FPGAs

Heterogeneous resources such as configurable logic blocks (CLBs), multiplier blocks (MULs) and ram blocks (RAMs) where millions of logic gates (a growing trend to implement larger and more complex functions) included have been added to field programmable gate arrays (FPGAs). And floorplanning for this, hierarchical approach is recognized as the most effective method. The FPGA architecture shows that CLBs hold the maximum quantity much more than other resources. Therefore, making a high utilization of them means an enhancement of the FPGA densities. This paper presents a three-phase floorplanning method for heterogeneous FPGAs. The proposed method can make the resource requirement of functional modules satisfied with a high resource utilization. First, we use a non-slicing floorplanning method to optimize the wirelength, however, in this phase, the satisfaction of resource requirements from functional modules might fail. Second, a min-cost-max-flow algorithm is used to tune the assignment of CLBs to functional modules, such that all the functional modules get CLB requirements satisfied. Finally, the MULs and RAMs are allocated to modules by a network flow model. The results show that about 7%-85% wirelength reduction is obtained, and CLB utilization is improved by about 25%.

Floorplan Design for Multimillion Gate FPGAs

Modern field-programmable gate arrays (FPGAs) have multimillions of gates and future generations of FPGAs will be even more complex. This means that floorplanning tools will soon be extremely important for the physical design of FPGAs. Due to the heterogeneous logic and routing resources of an FPGA, FPGA floorplanning is very different from the traditional floorplanning for application-specific integrated circuits. This paper presents the first FPGA-floorplanning algorithm targeted for FPGAs with heterogeneous resources (e.g., Xilinx's Spartan3 chips consisting of columns of configurable logic blocks, RAM blocks, and multiplier blocks). This algorithm can generate floorplans for Xilinx's XC3S5000 architecture (largest of the Spartan3 family) in a few minutes

WASMII: An MPLD with data-driven control on a virtual hardware

Through the use of an extended field programmable gate array (FPGA) technology, a large digital circuit can be realized on a relatively small amount of real hardware. Several configuration RAM modules are provided inside the FPGA chip, and the configuration of the gate array can be rapidly changed by replacing the active module. Data for configuration are transferred from an off-chip backup RAM to an unused configuration RAM module. A novel computation mechanism called the WASMII, which executes a target dataflow graph directly, can be proposed on the basis of this “virtual hardware.” A WASMII chip consists of the FPGA for virtual hardware and an additional mechanism to replace configuration RAM modules in a data-driven manner. Configuration data are preloaded in the order assigned in advance by a static scheduling preprocessor. By connecting a number of WASMII chips, a highly parallel system can be easily constructed.

A 209 K-transistor ECL gate array with RAM

The authors describe a gate array with an ECL (emitter-coupled-logic) cell structure for implementing a high-density configurable RAM. A unit based on a variable size cell is modified to achieve such a RAM. Every unit has an extra transistor buried under the power bus to eliminate area penalty. One memory bit is constructed using one buried transistor plus three transistors in a unit. An n-p-n transistor and a tap resistor load cell are employed for structural matching with the logic gates. Since the read current is supplied directly from the V/sub CC/ bus instead of the word line, the transistor size of the word-line driver is minimized. The standby and read currents are 120 mu A and 800 mu A, respectively. The decoder, sense amplifiers, and word-line drivers are implemented by logic gates. RAM size can be varied by each unit row; the bit increment is 144. The process employs double-polysilicon self-aligned technology with a silicide-base electrode of TiSi/sub 2/ and triple-layer metallization. The features of the gate array are listed. >