Configuration Memory Scrubbing Research Articles

Neutron Radiation Testing of RISC-V TMR Soft Processors on SRAM-Based FPGAs

Soft, configurable processors within FPGA designs are susceptible to SEUs. SEU mitigation techniques such as TMR and configuration memory scrubbing can be used to improve the reliability of soft processor designs. This paper presents the improvements in reliability of five different TMR soft processors within a neutron radiation environment. The TMR processors achieved up to a 75× improvement in reliability at the cost of potentially 4.8× resource utilization and an average 12.4% decrease in maximum frequency compared to the unmitigated designs. This work compares the metrics of reliability, power consumption, and performance among the default unmitigated processors and their TMR variations.

Configuration Memory Scrubbing of SRAM-Based FPGAs Using a Mixed 2-D Coding Technique

SRAM-based field-programmable gate array (FPGA) vendors typically integrate error correction codes (ECCs) into the configuration memory to assist designers in implementing scrubbing mechanisms. In most cases, these ECC schemes guarantee the correction of single- and double-bit errors per configuration frame but fail to correct upsets with higher multiplicity in a single frame caused by a single event. This phenomenon has been observed in modern commercial-off-the-shelf FPGAs. Bit interleaving schemes are used in some FPGA families to scatter the multiple upsets into more than one frame, but this does not fully resolve the problem of uncorrectable errors. In this article, we propose a configuration memory scrubbing approach for SRAM-based FPGA devices, which combines the embedded ECC logic with an interframe, interleaved parity code to build a mixed 2-D coding technique. The proposed technique improves the multiple-bit error correction capabilities of the on-chip ECC scheme while keeping the error correction latency and hardware cost low. The scrubbing concept has been validated under heavy-ion irradiation, where it succeeded in correcting all the single and multiple upsets observed during the radiation experiment.

An analysis of FPGA configuration memory SEU accumulation and a preventative scrubbing technique

Reliability in microelectronics is an important factor in high radiation environments, such as in space, particularly in SRAM-based FPGAs where a Single Event Upset (SEU) in the configuration memory can have drastic effects on the connections of implemented designs. As technology advances and components reduce in size with lower operating powers, SEUs can occur more frequently. An SEU in the configuration memory is permanent unless the associated bit is rewritten either by a full reconfiguration or configuration memory scrubbing. In this paper we discuss a phenomenon that we call secondary critical bits (SCBs), in which certain bits or frames have a chance of causing functional failures if an SEU already exists in the system without a functional failure, and a new metric, frame criticality that can be used for a more fine-grained analysis of a designs reliability. We present a novel frame based statistical double bit fault injection method to analyse the frame criticality in a feasible amount of time. Also presented is a passive configuration memory scrubbing scheme that offers greater protection against this phenomenon compared with traditional blind techniques with improvements up to 65%, for higher SEU rates and more sensitive components.

Fault-Tolerant FPGA-Based Nanosatellite Balancing High-Performance and Safety for Cryptography Application

With the growth of the nano-satellites market, the usage of commercial off-the-shelf FPGAs for payload applications is also increasing. Due to the fact that these commercial devices are not radiation-tolerant, it is necessary to enhance them with fault mitigation mechanisms against Single Event Upsets (SEU). Several mechanisms such as memory scrubbing, triple modular redundancy (TMR) and Dynamic and Partial Reconfiguration (DPR), can help to detect, isolate and recover from SEU faults. In this paper, we introduce a dynamically reconfigurable platform equipped with configuration memory scrubbing and TMR mechanisms. We study their impacts when combined with DPR, providing three different execution modes: low-power, safe and high-performance mode. The fault detection mechanism permits the system to measure the radiation level and to estimate the risk of future faults. This enables the possibility of dynamically selecting the appropriate execution mode in order to adopt the best trade-off between performance and reliability. The relevance of the platform is demonstrated in a nano-satellite cryptographic application running on a Zynq UltraScale+ MPSoC device. A fault injection campaign has been performed to evaluate the impact of faulty configuration bits and to assess the efficiency of the proposed mitigation and the overall system reliability.

Scrubbing-Aware Placement for Reliable FPGA Systems

Field Programmable Gate Arrays (FPGAs) provide complex embedded blocks to ease the development of high-performance computing systems for diverse area applications, including among others space, avionics and health. Although the rich set of features is ever expanding, there is one significant shortcoming of the SRAM-based FPGAs which concerns system designers for applications demanding high reliability: their vulnerability to Single Event Upsets (SEUs) which can cause system malfunction. In this work, we propose a placement approach to improve system reliability by reducing the execution time of configuration memory scrubbing, which can be used in conjunction with other reliability mechanisms proposed in the literature. The proposed placement approach is based on i) an automated floorplanning process to shape and locate the design region(s) and ii) a modified version of the Simulated Annealing placement algorithm aiming to reduce the scrubbing time. First, we performed a set of experiments with three QUIP benchmarks to demonstrate the efficiency of the proposed approach at different device utilization levels. Moreover, we illustrated its effectiveness for three different fault tolerance schemes, where scrubbing plays a different role in each one: i) a TMR microcontroller combined with scrubbing, ii) a soft processor protected by a low-cost mitigation scheme including scrubbing and checkpointing, iii) a JPEG encoder protected by a prioritized scrubbing scheduling scheme based on module criticality levels. The experimental results showed that the proposed approach improves system reliability in all the above schemes by reducing critical timing parameters, such as mean-time-to-detect and mean-time-to-repair. This reduction leads to a modest or high reliability improvement depending on the role of scrubbing in the adopted fault tolerance (FT) scheme.

Reliability Calculation With Respect to Functional Failures Induced by Radiation in TMR Arm Cortex-M0 Soft-Core Embedded Into SRAM-Based FPGA

This paper presents comparative results from fault injection (FI) and heavy ions accelerated irradiation on a Xilinx 7 series static RAM (SRAM)-based field-programmable gate array (FPGA) for a soft-core microprocessor mitigated by triple modular redundancy (TMR) with different levels of granularity. The Arm Cortex-M0 soft-core processor executing two software applications is employed as a case study. The TMR implementation is automatically generated from synthesized netlist and includes coarse and fine grain variants. Apart from the TMR mitigation, the configuration memory scrubbing is used as implemented by the engine natively available on Xilinx 7 series FPGAs. Experiments with FI and heavy ions allow analyzing the effectiveness of the automated TMR mitigation combined with memory scrubbing and also to analyze the consistency of reliability metrics from FI and heavy ions. The dynamic cross section of the design was improved up to 4.5 times according to the implemented TMR granularity and when associated with the configuration memory scrubbing.

Fine-Grained Module-Based Error Recovery in FPGA-Based TMR Systems

Space processing applications deployed on SRAM-based Field Programmable Gate Arrays (FPGAs) are vulnerable to radiation-induced Single Event Upsets (SEUs). Compared with the well-known SEU mitigation solution—Triple Modular Redundancy (TMR) with configuration memory scrubbing—TMR with module-based error recovery (MER) is notably more energy efficient and responsive in repairing soft-errors in the system. Unfortunately, TMR-MER systems also need to resort to scrubbing when errors occur between sub-components, such as in interconnection nets, which are not recovered by MER. This article addresses this problem by proposing a fine-grained module-based error recovery technique, which can localize and correct errors that classic MER fails to do without additional system hardware. We evaluate our proposal via fault-injection campaigns on three types of circuits implemented in Xilinx 7-Series devices. With respect to scrubbing, we observed reductions in the mean time to repair configuration memory errors of between 48.5% and 89.4%, while reductions in energy used recovering from configuration memory errors were estimated at between 77.4% and 96.1%. These improvements result in higher reliability for systems employing TMR with fine-grained reconfiguration than equivalent systems relying on scrubbing for configuration error recovery.

Reliability Analysis of Field-Programmable Gate-Array-Based Space Computer Architectures

This paper presents an analysis of the radiation tolerance of field-programmable gate-array-based space computers. The primary failure mechanism studied in this paper is single-event effects due to high-energy ionizing radiation. The analysis is performed on the most common architectures deployed on field-programmable gate-array-based systems including simplex, triple modular redundant, inclusion of spares, and configuration memory scrubbing. The reliability of each system is modeled using a Markov chain to predict its mean time to failure. Orbital dependencies are discussed in addition to a comparison of reliability across different process nodes.

Benefits of Complementary SEU Mitigation for the LEON3 Soft Processor on SRAM-Based FPGAs

A variety of mitigation techniques have been demonstrated to reduce the sensitivity of FPGA designs to soft errors. Without mitigation, SEUs can cause failure by altering the logic, routing, and state of a design operating on an SRAM-based FPGA. Various combinations of SEU mitigation and repair techniques are applied to the LEON3 soft-core processor to study the effects and complementary nature of each technique. This work focuses on Triple modular redundancy (TMR), configuration memory (CRAM) scrubbing, and internal block memory (BRAM) scrubbing. All mitigation methods demonstrate some improvement in both fault injection and neutron radiation testing. Results in this paper show complementary SEU mitigation techniques working together to improve fault-tolerance. The results also suggest that fault injection can be a good way to estimate the cross section of a design before going to a radiation test. TMR with CRAM scrubbing demonstrates a $27\times $ improvement whereas TMR with both CRAM and BRAM scrubbing demonstrates approximately a $50\times $ improvement.

A Hybrid Fault-Tolerant LEON3 Soft Core Processor Implemented in Low-End SRAM FPGA

In this work we implemented a hybrid fault-tolerant LEON3 soft-core processor in a low-end FPGA (Artix-7) and evaluated its error detection capabilities through neutron irradiation and fault injection in an incremental manner. The error mitigation approach combines the use of SEC/DED codes for memories, a hardware monitor to detect control-flow errors, software-based techniques to detect data errors and configuration memory scrubbing with repair to avoid error accumulation. The proposed solution can significantly improve fault tolerance and can be fully embedded in a low-end FPGA, with reduced overhead and low intrusiveness.

Increasing Radiation Tolerance of Field-Programmable-Gate-Array-Based Computers Through Redundancy and Environmental Awareness

Radiation-tolerant computing is of great importance to the aerospace community because future missions demand more computational power. Of special interest to the aerospace community are flight computers implemented on static random-access-memory-based field-programmable gate arrays. Such computer systems allow the in-flight reconfiguration of hardware that enables the practical deployment of truly reconfigurable computers. However, commercial static random-access-memory-based field-programmable gate arrays are uniquely susceptible to ionizing radiation. This paper introduces a computer architecture for static random-access-memory-based field-programmable gate arrays that resists failures caused by ionizing radiation. The approach extends the widely accepted fault mitigation practice of triple modular redundancy and configuration memory scrubbing by adding spare circuitry and environmental awareness through an ionizing radiation sensor. This paper describes the design of the system in addition to a theoretical analysis of its reliability using a Markov model and empirical analysis using a fault injector. A full system prototype is presented that includes a custom radiation sensor and a computer system implemented on a Xilinx Virtex-6 field-programmable gate array. Both the theoretical analysis and laboratory testing show the approach to be significantly more reliable than field-programmable-gate-array-based computers using only triple modular redundancy and scrubbing.

System Design Framework and Methodology for Xilinx Virtex FPGA Configuration Scrubbers

SRAM-based FPGAs, like Xilinx Virtex series, are susceptible to ionizing radiation and require configuration memory scrubbing in order to be used in harsh radiation environments. The scrubbing is typically performed by a scrubber device external to the FPGA (via configuration ports). A design framework and methodology for such scrubbers is described in this paper. The framework is based on SystemC modeling language and includes a Scrubber Model, a Supervisor Model, an FPGA Model and a Fault Injector Model. The framework allows simulating scrubbing algorithms and the configuration links at frame level or physical levels (SelectMAP or JTAG). The designer can define scrub and fault injection rates, frame and fault lists, fault detection methods, etc. With the proposed framework and methodology, the designer can explore the scrubber design space in advance to any hardware implementation.

Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers

SRAM-based FPGAs are in-field reconfigurable an unlimited number of times. This characteristic, together with their high performance and high logic density, proves to be very convenient for a number of ground and space level applications. One drawback of this technology is that it is susceptible to ionizing radiation, and this sensitivity increases with technology scaling. This is a first order concern for applications in harsh radiation environments, and starts to be a concern for high reliability ground applications. Several techniques exist for coping with radiation effects at user application. In order to be effective they need to be complemented with configuration memory scrubbing, which allows error mitigation and prevents failures due to error accumulation. Depending on the radiation environment and on the system dependability requirements, the configuration scrubber design can become more or less complex. This paper classifies and presents current and novel design methodologies and architectures for SRAM-based FPGAs, and in particular for Xilinx Virtex-4QV/5QV, configuration memory scrubbers.

고속 데이터 처리를 위한 과학기술위성 3호 대용량 메모리 유닛의 개념 설계

본 연구에서는 과학기술위성 2호와 비교 했을 때 고속의 데이터를 처리하고 대용량의 메모리를 관리해야하는 요구사항을 만족하기 위한 과학기술위성 3호 대용량 메모리 유닛의 설계 내용에 대해서 나타내었다. 이러한 요구사항을 만족하기 위해서, 두 개의 탑재체에서 각각 최대 100Mbps로 수신되는 데이터와 32Gb의 대용량 메모리를 처리하고 관리하는 역할을 FPGA가 직접 담당 하도록 설계하였다. 사용된 FPGA는 동작 속도가 빠르고 게이트 수가 많은 SRAM 기반의 Xilinx FPGA로써 우주 환경에서의 SEU를 극복하기 위해서 TMR 기법과 스크러빙 기법을 적용하고자 한다. This paper describes the conceptual design of mass memory unit for high speed data processing and mass memory management in the STSAT-3 compared to that of STSAT-2. The FPGA directly controls the data receiving from two payloads with the maximum 100Mbps speed and 32Gb mass memory management to satisfy these requirements. We used SRAM-based FPGA from XILINX having fast operating speed and large logic cells. Therefore, the Triple Modular Redundancy(TMR) and configuration memory scrubbing techniques will also be used to protect FPGA from Single Event Upset(SEU) in space.

Enhanced Reliability of Finite-State Machines in FPGA Through Efficient Fault Detection and Correction

SRAM based FPGA are subjected to ion radiation in many operating environments. Following the current trend of shrinking device feature size & increasing die area, newer FPGA are more susceptible to radiation induced errors. Single event upsets (SEU), (also known as soft-errors) account for a considerable amount of radiation induced errors. SEU are difficult to detect & correct when they affect memory-elements present in the FPGA, which are used for the implementation of finite state machines (FSM). Conventional practice to improve FPGA design reliability in the presence of soft-errors is through configuration memory scrubbing, and through component redundancy. Configuration memory scrubbing, although suitable for combinatorial logic in an FPGA design, does not work for sequential blocks such as FSM. This is because the state-bits stored in flip-flops (FF) are variable, and change their value after each state transition. Component redundancy, which is also used to mitigate soft-errors, comes at the expense of significant area overhead, and increased power consumption compared to nonredundant designs. In this paper, we propose an alternate approach to implement the FSM using synchronous embedded memory blocks to enhance the runtime reliability without significant increase in power consumption. Experiments conducted on various benchmark FSM show that this approach has higher reliability, lower area overhead, and consumes less power compared to a component redundancy technique.