Neutron Radiation Testing of RISC-V TMR Soft Processors on SRAM-Based FPGAs

Abstract

Soft, configurable processors within FPGA designs are susceptible to SEUs. SEU mitigation techniques such as TMR and configuration memory scrubbing can be used to improve the reliability of soft processor designs. This paper presents the improvements in reliability of five different TMR soft processors within a neutron radiation environment. The TMR processors achieved up to a 75× improvement in reliability at the cost of potentially 4.8× resource utilization and an average 12.4% decrease in maximum frequency compared to the unmitigated designs. This work compares the metrics of reliability, power consumption, and performance among the default unmitigated processors and their TMR variations.