Errors In Configuration Memory Research Articles

Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs

There are many platforms and tools based on field-programmable gate array (FPGA) devices oriented to facilitate the reliability estimation of digital designs, but they are usually focused only on configuration memory errors since the configuration memory represents the majority of the memory elements in an FPGA. However, an FPGA-based platform could also be exploited to support the emulation of transient and permanent errors for designs intended to work in application-specific integrated circuits (ASICs) or radiation-hardened devices such as antifuse FPGAs. In this context, the obtention of a particular set of bits to flip is required to be able to emulate these error models. The main difficulty of this approach lies in determining the mentioned set of bits, which is due to the unavailability of a public description of the bitstream and the lack of FPGA architecture details. To help with this issue, we present a methodology to determine specific configuration memory bits from SRAM-based FPGAs that, when flipped, emulate permanent or transient upsets in any flip-flop element of the design under test. This methodology is proved in recent FPGA technologies and provides great control and precision in reliability experiments for harsh environments.

Reliability Analysis of the SHyLoC CCSDS123 IP Core for Lossless Hyperspectral Image Compression Using COTS FPGAs

Hyperspectral images can comprise hundreds of spectral bands, which means that they can represent a large volume of data difficult to manage with the available on-board resources. Lossless compression solutions are interesting for reducing the amount of information stored or transmitted while preserving it at the same time. The Hyperspectral Lossless Compressor for space applications (SHyLoC), which is part of the European Space Agency (ESA) IP core’s library, has been demonstrated to meet the requirements of space missions in terms of compression efficiency, low complexity and high throughput. Currently, there is a trend to use Commercial Off-The-Shelf (COTS) on-board electronic devices on small satellites. Moreover, commercial Field-Programmable Gate Arrays (FPGAs) have been used in a number of them. Hence, a reliability analysis is required to ensure the robustness of the applications to Single Event Upsets (SEUs) in the configuration memory. In this work, we present a reliability analysis of this hyperspectral image compression module as a first step towards the development of ad-hoc fault-tolerant protection techniques for the SHyLoC IP core. The reliability analysis is performed using a fault-injection-based experimental set-up in which a hardware implementation of the Consultative Committee for Space Data Systems (CCSDS) 123.0-B-1 lossless compression standard is tested against configuration memory errors in a Xilinx Zynq XC7Z020 System-on-Chip. The results obtained for unhardened and redundancy-based protected versions of the module are put into perspective in terms of area/power consumption and availability/protection coverage gained to provide insight into the development of more efficient knowledge-based protection schemes.

FMER: An Energy-Efficient Error Recovery Methodology for SRAM-Based FPGA Designs

This paper introduces frame- and module-based configuration memory error recovery (FMER), that is, a FMER technique targeting triple modular redundant (TMR) designs that are realized on SRAM-based FPGAs. Module-based configuration memory (CM) error recovery (MER) is used to reconfigure on demand the CM of faulty TMR modules, whereas the remaining CM of the device recovers from soft errors with periodic scrubbing. We derive reliability, availability, and power consumption models of TMR designs that incorporate FMER, MER, blind scrubbing, and no recovery at all, and show that FMER is particularly beneficial for missions that require high reliability or availability subject to a low-energy budget.

Scheduling configuration memory error checks to improve the reliability of FPGA‐based systems

Field-programmable gate arrays are susceptible to radiation-induced single event upsets. These are commonly dealt with using triple modular redundancy (TMR) and module-based configuration memory error recovery (MER). By triplicating components and voting on their outputs, TMR helps localise configuration memory errors, and by reconfiguring faulty components, MER swiftly corrects them. However, the order in which TMR voters are checked inevitably impacts the overall system reliability. In this study, the authors outline an approach for computing the reliability of TMR–MER systems that consist of finitely many components. They demonstrate that system reliability is improved when the more vulnerable components are checked more frequently than when they are checked in round-robin order. They propose a genetic algorithm for finding a voter checking schedule that maximises the reliability of TMR–MER systems. Results indicate that the mean time to failure (MTTF) of these systems can be increased by up to 400% when variable-rate voter checking (VRVC) is used instead of round robin. They show that VRVC achieves 15–23% increase in MTTF with a 10× reduction in checking frequency to reduce system power. They also found that VRVC detects errors 44% faster on average than round robin.

Protecting Image Processing Pipelines against Configuration Memory Errors in SRAM-Based FPGAs

Image processing systems are widely used in space applications, so different radiation-induced malfunctions may occur in the system depending on the device that is implementing the algorithm. SRAM-based FPGAs are commonly used to speed up the image processing algorithm, but then the system could be vulnerable to configuration memory errors caused by single event upsets (SEUs). In those systems, the captured image is streamed pixel by pixel from the camera to the FPGA. Certain local operations such as median or rank filters need to process the image locally instead of pixel by pixel, so some particular pixel caching structures such as line-buffer-based pipelines can be used to accelerate the filtering process. However, an SRAM-based FPGA implementation of these pipelines may have malfunctions due to the mentioned configuration memory errors, so an error mitigation technique is required. In this paper, a novel method to protect line-buffer-based pipelines against SRAM-based FPGA configuration memory errors is presented. Experimental results show that, using our protection technique, considerable savings in terms of FPGA resources can be achieved while maintaining the SEU protection coverage provided by other classic pipeline protection schemes.

Reconfiguration Control Networks for FPGA-based TMR systems with modular error recovery

Field-Programmable Gate Arrays (FPGAs) provide ideal platforms for meeting the computational requirements of future space-based processing systems. However, FPGAs are susceptible to radiation-induced Single Event Upsets (SEUs). Techniques for dynamically reconfiguring corrupted modules of Triple Modular Redundant(TMR) components are well known. However, most of these techniques utilize resources that are themselves susceptible to SEUs to transfer reconfiguration requests from the TMR voters to a central reconfiguration controller. This paper evaluates the impact of these Reconfiguration Control Networks (RCNs) on the system’s reliability and performance. We provide an overview of RCNs reported in the literature and compare them in terms of dependability, scalability and performance. Most importantly, we compare the performance of soft networks with that of a hard network that utilizes the Internal Configuration Access Port(ICAP) available in advanced Xilinx devices to periodically read the TMR voter states. We have implemented our designs on a Xilinx Artix-7 FPGA to assess the resulting resource utilization and performance as well as to evaluate their soft error vulnerability using analytical and fault injection techniques. Results show that, of the RCN topologies studied, the ICAP-based approach is the most reliable despite having the highest network latency. We also conclude that a module-based recovery approach is less reliable than scrubbing unless the RCN is implemented with redundancy and repaired when it suffers from configuration memory errors.

Fine-Grained Module-Based Error Recovery in FPGA-Based TMR Systems

Space processing applications deployed on SRAM-based Field Programmable Gate Arrays (FPGAs) are vulnerable to radiation-induced Single Event Upsets (SEUs). Compared with the well-known SEU mitigation solution—Triple Modular Redundancy (TMR) with configuration memory scrubbing—TMR with module-based error recovery (MER) is notably more energy efficient and responsive in repairing soft-errors in the system. Unfortunately, TMR-MER systems also need to resort to scrubbing when errors occur between sub-components, such as in interconnection nets, which are not recovered by MER. This article addresses this problem by proposing a fine-grained module-based error recovery technique, which can localize and correct errors that classic MER fails to do without additional system hardware. We evaluate our proposal via fault-injection campaigns on three types of circuits implemented in Xilinx 7-Series devices. With respect to scrubbing, we observed reductions in the mean time to repair configuration memory errors of between 48.5% and 89.4%, while reductions in energy used recovering from configuration memory errors were estimated at between 77.4% and 96.1%. These improvements result in higher reliability for systems employing TMR with fine-grained reconfiguration than equivalent systems relying on scrubbing for configuration error recovery.

Error Detection Technique for a Median Filter

In digital image processing systems, the acquisition stage may capture impulsive noise along with the image. This physical phenomenon is commonly referred to as “salt-and-pepper” noise. The median filter is a nonlinear image processing operation used to remove this impulsive noise from images. This digital filter can be implemented in hardware to speed up the algorithm. However, an SRAM-based field-programmable gate array implementation of this filter is then susceptible to configuration memory bit flips induced by single event upsets, so a protection technique is needed for critical applications in which the proper filter operation must be ensured. In this paper, a fault-tolerant implementation of the median filter is presented and studied in-depth. Our protection technique checks if the median output is within a dynamic range created with the remaining nonmedian outputs. An output error signal is activated if a corrupted image pixel is detected, then a partial or complete reconfiguration can be performed to remove the configuration memory error. Experimental results show that our technique detects enough corrupted pixels in an image to prevent 91% of the corrupted images from being erroneously sent to the next image processing operation. This high error detection rate is achieved introducing only a 35% of additional resource overhead.

Multibit Fault Injection for Field-Programmable Gate Arrays with Simple, Portable Fault Injector

Static random-access-memory-based field-programmable gate array devices are an attractive option for onboard data processing in space systems due to higher computational capabilities and a lower power envelope than traditional processing devices. However, field-programmable gate arrays present unique reliability verification challenges because single-event upsets can trigger both data errors and configuration memory errors, which may cause deviations from the expected system functionality. To evaluate system reliability, traditional fault-injection testing uses numerous test vectors to observe the effects induced by a change of a single configuration memory bit at a time. This single-bit fault-injection methodology provides high fault coverage and testing repeatability, but it requires a long fault-injection time due to the large number of test vectors required to verify the entire design’s functionality. Long injection times are further exacerbated as configuration memory size and design complexity increase. To shorten injection time, a Simple, Portable Fault Injector platform is proposed for field-programmable gate arrays used in tandem with a novel multibit fault-injection methodology that modifies multiple configuration memory bits, referred to as a batch, during each test. The proposed methodology is optimized to efficiently detect the faulty bits within a batch, adaptively select the optimal batch size, and optimize the fault-injection sequence based on the design’s placement. Using relevant case studies, Simple, Portable Fault Injector for field-programmable gate arrays augmented with multibit fault-injection methodology reveals up to 50 times the speedup in fault-injection time.

SEU-SECURE PARITY PREDICTION MULTIPLIER ON SRAM-BASED FPGAs

Modern SRAM-based field programmable gate array (FPGA) devices offer high capability in implementing satellites and space systems. Unfortunately, these devices are extremely sensitive to various kinds of unwanted effects induced by space radiations especially single-event upsets (SEUs) as soft errors in configuration memory. To face this challenge, a variety of soft error mitigation techniques have been adopted in literature. In this paper, we describe an area-efficient multiplier architecture based on SRAM-FPGA that provides the self-checking capability against SEU faults. The proposed design approach, which is based on parity prediction, is able to concurrently detect the SEU faults. The implementation results of the proposed architecture reveal that the average area and delay overheads are respectively 25% and 34% in comparison with the plain version while the conventional duplication with comparison (DWC) architecture imposes 117% and 22% overheads. Moreover, the single and multi-upset fault injection experiments reveal that the proposed architecture averagely provides the failure coverage of 83% and 79% while the failure coverage of the duplicated structure is 85% and 84%, respectively for SEU and MEU faults.