Abstract
Hyperspectral images can comprise hundreds of spectral bands, which means that they can represent a large volume of data difficult to manage with the available on-board resources. Lossless compression solutions are interesting for reducing the amount of information stored or transmitted while preserving it at the same time. The Hyperspectral Lossless Compressor for space applications (SHyLoC), which is part of the European Space Agency (ESA) IP core’s library, has been demonstrated to meet the requirements of space missions in terms of compression efficiency, low complexity and high throughput. Currently, there is a trend to use Commercial Off-The-Shelf (COTS) on-board electronic devices on small satellites. Moreover, commercial Field-Programmable Gate Arrays (FPGAs) have been used in a number of them. Hence, a reliability analysis is required to ensure the robustness of the applications to Single Event Upsets (SEUs) in the configuration memory. In this work, we present a reliability analysis of this hyperspectral image compression module as a first step towards the development of ad-hoc fault-tolerant protection techniques for the SHyLoC IP core. The reliability analysis is performed using a fault-injection-based experimental set-up in which a hardware implementation of the Consultative Committee for Space Data Systems (CCSDS) 123.0-B-1 lossless compression standard is tested against configuration memory errors in a Xilinx Zynq XC7Z020 System-on-Chip. The results obtained for unhardened and redundancy-based protected versions of the module are put into perspective in terms of area/power consumption and availability/protection coverage gained to provide insight into the development of more efficient knowledge-based protection schemes.
Highlights
On-board hyperspectral image compression has been adopted by several space missions since it implies a significant data volume reduction [1]
Core protected with a Dual Modular Redundancy (DMR) scheme, and a third version protected with a Triple Modular Redundancy (TMR) scheme have been chosen
This is because the Intellectual Property (IP) core requires more internal memory to process larger images, which has a direct impact on the power consumption of the design
Summary
On-board hyperspectral image compression has been adopted by several space missions since it implies a significant data volume reduction [1]. A modification in the behavior of the on-board hyperspectral image compression module may lead to the corruption of several samples during the decompression process (see Figure 1) For this reason, the design implemented in the FPGA has to be protected against soft errors to avoid malfunctions. The CCSDS-123 Intellectual Property (IP) core has been implemented on the SRAM-based FPGA part of a Xilinx Zynq XC7Z020 System-on-Chip and tested against configuration memory errors through the mentioned fault-injection-based experimental set-up From these experiments, the intrinsic reliability of the unprotected design is estimated to get an insight into its behavior in a real deployed satellite.
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