FMER: An Energy-Efficient Error Recovery Methodology for SRAM-Based FPGA Designs

Abstract

This paper introduces frame- and module-based configuration memory error recovery (FMER), that is, a FMER technique targeting triple modular redundant (TMR) designs that are realized on SRAM-based FPGAs. Module-based configuration memory (CM) error recovery (MER) is used to reconfigure on demand the CM of faulty TMR modules, whereas the remaining CM of the device recovers from soft errors with periodic scrubbing. We derive reliability, availability, and power consumption models of TMR designs that incorporate FMER, MER, blind scrubbing, and no recovery at all, and show that FMER is particularly beneficial for missions that require high reliability or availability subject to a low-energy budget.