A fault injection platform for the analysis of soft error effects in FPGA soft processors

Abstract

Soft processors in SRAM-based FPGAs are gaining acceptance as enabling technology for building embedded systems in several market domains, even for critical applications such as space, transportation and medical devices. However, due to the high vulnerability of SRAM-based FPGAs to single-event upsets (SEUs), which is expected to be aggravated in the future, as FPGA devices are moving aggressively to the nanometer regime, the hardening of soft processors against soft errors will become a major design issue especially for critical applications. Most SEU mitigation approaches proposed in the past are based on the triplication or duplication techniques, thus imposing significant area and performance overheads. A more detailed analysis of the soft error sensitivity of FPGA soft processor and their faulty behavior will enable the development of efficient, low-cost hardening techniques. To this end, we present a fault injection platform based on an open-source CAD framework (RapidSmith) for the analysis of soft error effects in Xilinx FPGA soft processors. Our platform supports the estimation of soft error sensitivity per configuration bit/frame, processor component and benchmark. An on-chip microcontroller is used to inject and correct soft errors in the configuration memory and monitor target processor behavior. It includes a custom peripheral to monitor and record specific processor signals (e.g. exception signals, performance counters) which may manifest the effects of soft errors. The proposed platform is demonstrated through an extensive fault injection campaign in the Leon3 soft processor. The novelty of the framework is it's availability as open-source fault-injection tool designed to target soft processors and the introduction of fault identification by using performance counter.