An Automated FPGA-Based Fault Injection Platform for Granularly-Pipelined Fault Tolerant CORDIC

Abstract

Augment of integration and complexity makes VLSI circuits more sensitive to errors. Also, soft errors caused by Single Event Upset (SEU) have become a significant threat to modern electronic systems. Therefore, the demand of high reliability on modern electronic systems keeps increasing. Aiming at reliability evaluation of fault tolerant very large scale integrated circuits implemented on SRAM-based FPGA, an automated fault injection platform via Internal Configuration Access Port (ICAP) for rapid fault injection is presented in this paper. We adopt a granularly-pipelined fault tolerant CORDIC processor as the Design Under Test (DUT), and a C++ script is deployed for the external fault injection control environment and automating the fault injection procedure. The proposed method can achieve quantities of repeating fault injection tests and is suitable for any fault tolerant design implemented in SRAM-Based FPGA.