An Automated Fault Injection Platform for Fault Tolerant FFT Implemented in SRAM-Based FPGA

Abstract

Soft errors caused by Single Event Upset (SEU) has become a significant threat to modern electronic systems. Aiming at reliability evaluation of fault tolerant very large scale integrated circuits implemented on SRAM-based FPGA, an automated fault injection platform via Internal Configuration Access Port (ICAP) for rapid fault injection is presented in this paper. We adopt a fault tolerant FFT processor as the Design Under Test (DUT), and a C++ application is deployed for the external fault injection control environment and automating the fault injection procedure. The proposed method can achieve quantities of repeating fault injection tests and is suitable for any fault tolerant design implemented in SRAM-Based FPGA. In this paper, we through a large number of experiments to find the critical bit which can support fault tolerant of FFT processor.