Configurable Logic Research Articles

Fuzzy Propositional Configuration Logics

We introduce and investigate a weighted propositional configuration logic over De Morgan algebras. This logic is able to describe software architectures with quantitative features especially the uncertainty of the interactions that occur in the architecture. We deal with the equivalence problem of formulas in our logic by showing that every formula can be written in a specific form. Surprisingly, there are formulas which are equivalent only over specific De Morgan algebras. We provide examples of formulas in our logic which describe well-known software architectures equipped with quantitative features such as the uncertainty and reliability of their interactions.

Cryptocurrencies have arrived, but are we ready? Unveiling cryptocurrency adoption recipes through an SEM-fsQCA approach

PurposeThe purpose of this study is to investigate consumers’ cryptocurrency adoption through the unified theory of acceptance and use of technology (UTAUT) and complexity theory.Design/methodology/approachBy using a purposive sampling method, a configurational model was developed and a questionnaire-based survey was conducted to gather responses from a Malaysian sample. A total of 223 responses were obtained. Partial least square structural equation modeling (PLS-SEM) and fuzzy set qualitative comparative analysis (fsQCA) were adopted to analyze the data.FindingsThe PLS-SEM indicated that performance expectancy, effort expectancy, social influence and affinity for technology interaction were positive cryptocurrency adoption predictors, whereas regulation was a negative predictor. Based on the fsQCA, cryptocurrency adoption could be explained by six configurational paths, which comprised combinations of the proposed causal conditions: the UTAUT factors (performance expectancy, effort expectancy, facilitating condition and social influence), environmental factor (regulation) and individual factors (financial knowledge and affinity for technology interaction).Research limitations/implicationsThis study offers contributions to the theoretical body of knowledge by articulating the relevance of extended UTAUT and extending the established UTAUT model by integrating external environment and personal factors, also showing the linear and nonlinear interplays of performance expectancy, effort expectancy, facilitating conditions, social influence, regulation, financial knowledge and affinity for technology interaction.Practical implicationsThe findings facilitated practitioners’ (cryptocurrency brokers, governments and businesses) fostering of cryptocurrency adoption through the joint consideration of different factors. The factors spanned technological attributes and individual characteristics to regulation. Practitioners should acknowledge that different combinations of the aforementioned antecedents can be equally effective to increase cryptocurrency adoption. The findings suggested that these causal conditions should be considered holistically and that there is no best predictor.Social implicationsIn social terms, the research is expected to contribute to the dissemination of cryptocurrencies and help governments and central banks to develop, regulate and supervise digital currencies, as well as in the implementation of a digital currency ecosystem aligned with sustainable development goals. Economically, the results might foster a high cryptocurrency adoption rate and stimulate crypto-token-based business models and investment opportunities that present new means of revenue generation at individual, organizational and national levels.Originality/valueThis study offers unique perspectives for the body of knowledge and practice in the cryptocurrency domain, using both symmetric and asymmetric methodologies, by delineating the configurational logic involving technological capabilities, social influences, regulation and individual characteristics in facilitating more efficacious dissemination of cryptocurrencies.

The Need for Speed and Energy Efficiency in Genome Analysis

The Need for Speed and Energy Efficiency in Genome Analysis

Verification and Validation of ITER Interlock System Fast Architecture According to IEC 61508 Standard

The ITER Interlock Control System (ICS) requires the application of the IEC 61508 standard for all mission-critical (known as investment protection) control functions. Such functions must detect the events of the integrated physical processes and distribute them to the actuators with hard real-time constraints on the order of milliseconds or even microseconds. Systems able to achieve these timing requirements are often bespoke FPGA-based solutions, which are a well-known challenge to IEC 61508 processes. However, to minimize the variety of components and simplify the procurement process for an international supplier base, ITER decided to standardize the use of Commercial Off-The-Shelf (COTS) devices. The COTS selected for the ICS was the FPGA-based CompactRIO NI 9159 chassis (and several adapter I/O modules), provided by National Instruments (NI). This COTS requires the use of a high-level language (LabVIEW-FPGA) and the associated integrated development tools to develop the FPGA functionality. Therefore, it is necessary to ensure the required assurance that a COTS device is of sufficient quality, fit for purpose, and can be properly integrated into an investment protection control loop with the necessary level of systematic capability during the development process. This paper describes in detail the method ITER uses to perform the verification and validation according to the IEC 61508 standard recommendations, for the logic configuration generated by LabVIEW-FPGA for these COTS, after the compilation of high-level language sources designed during the development.

Ferroelectric topologically configurable multilevel logic unit

Multilevel devices demonstrating switchable polarization enable us to efficiently realize neuromorphic functionalities including synaptic plasticity and neuronal activity. Here we propose using the ferroelectric logic unit comprising multiple nanodots disposed between two electrodes and coated by the dielectric material. We devise the integration of the ferroelectric logic unit, providing topologically configurable non-binary logic into a gate stack of the field-effect transistor as an analog-like device with resistive states. By controlling the charge of the gate, we demonstrate the various routes of the topological switchings between different polarization configurations in ferroelectric nanodots. Switching routes between different logic levels are characterized by hysteresis loops with multiple branches realizing specific interconnectivity regimes. The switching between different types of hysteresis loops is achieved by the variation of external fields and temperature. The devised ferroelectric multilevel devices provide a pathway toward the novel topologically-controlled implementation of discrete synaptic states in neuromorphic computing.

CLB-Based Development of BiSS-C Interface Master for Motor Encoders

Encoder interfaces should be operated in real time with high precision and fast processing for industrial motor control systems. The continuous bidirectional serial synchronous (BiSS-C) interface is an open-source serial communication protocol designed for motor encoders and is suitable for industrial purposes because of its fast serial communication speed. In this study, we propose a method for developing a BiSS-C interface master for a motor encoder slave, using only the configurable logic block (CLB) peripheral integrated into TI microcontroller units. By analyzing the detailed operation protocol of the BiSS-C interface, we create the truth and state tables for logic circuits and finite state machines, which are required for the BiSS-C interface master. Then, by programming the CLB based on the created truth and state tables, we implement the master clock, serial peripheral interface (SPI) clock, and operational process for the master. This approach is cost-efficient because additional hardware components, such as a field-programmable gate array or a complex programmable logic device, are not required for the master implementations. The developed method can be immediately applied to developing the masters for other BiSS-C encoders with different specifications, which is certainly necessary for a motor drive development and test. By building an AC motor control system with the developed master and performing various experiments, we verify the performance and practical usefulness of the developed BiSS-C interface master. The maximum master clock frequency without any CRC errors is achieved by 6.25 MHz, which can cope with more than 20 kHz motor control cycle frequency. The usefulness is demonstrated by showing the motor speed and position control performance that are acceptable in real applications.

RETRACTED: Express Data Processing on FPGA: Network Interface Cards for Streamlined Software Inspection for Packet Processing

Modern computers’ network interface cards (NICs) are undergoing changes in order to handle greater data rates and assist with scaling problems caused by general-purpose CPU technology. The inclusion of programmable accelerators to the NIC’s data channel is one of the ongoing improvements that is particularly intriguing since it gives the accelerator the chance to take on a portion of the CPU’s network packet processing duties. Accelerators are frequently developed using platforms like field-programmable gate arrays because packet processing operations have severe latency requirements (FPGAs). When implementing packet processing activities, FPGAs’ gain for through put is the number of data packets being successfully sent per second and latency is the actual time those packets take. However, due to their restricted resources, programming may need to be shared throughout a variety of applications. We provide hXDP, a software solution for FPGAs that targets the Linux eXpress Data Path and performs packet processing functions outlined with the eBPF technology. While maintaining performance on par with top-tier CPUs, hXDP only uses a tiny portion from the field programmable gate arrays, which are semiconductor devices that are based around a matrix of configuration logic blocks (CLB) connected over programmable interconnects. However, we demonstrate that when aiming towards a purpose-built FPGA architecture, many extended Berkeley packet filters (eBPF) allow programmers to use Berkeley packet filter byte code that makes use of certain kernel resources and instruction set architecture, to collocate and even eliminate, with considerably productivity and effectiveness. On an FPGA NIC, we implement hXDP and test its effectiveness using authentic eBPF programmes from the real world. Our version consumes 15% of the FPGA resources and operates at 156.25 MHz. This can constantly change and lead to the act of identification, inspection, extraction, and manipulation so that a network may make more intelligent management decisions.

Ripple-Free Multiphase Interleaved Stacked Converter for High-Power Applications

A novel control technique that guarantees a ripple-free output current and voltage of a dc–dc multiphase staked interleaved converter is proposed. The conventional multiphase interleaved converters have been extensively used in various applications. However, ripple cancellation in these converters solely depends on the number of phases and can only be achieved at specific duty cycles. On the other hand, wide-range and ripple-free output are important paramount features for many modern applications. Therefore, the presented converter aims to combine the advantages of both the multiphase interleaved and the stacked converters into a single-unit converter suitable for high-power applications. Ripple-free output current/voltage is always guaranteed regardless of the number of phases and duty cycle values. This feature is accomplished by adding a fractionally-rated phase-leg to the conventional multiphase interleaved converter and modulating it with the proposed control approach. The configurable logic block, a state-of-the-art tool developed by Texas Instruments, is utilized to reduce the hardware size of the entire conversion system while increasing its speed and flexibility. Extensive simulation studies are carried out to confirm the functionality of the proposed control scheme. A laboratory porotype is developed to validate the effectiveness of the proposed control method experimentally. With only a few more components, significant reductions in output ripples are achieved.

Soft Error Sensitivity Analysis Based on 40 nm SRAM-Based FPGA

Soft errors induced by radiation are the major reliability threat for SRAM-based field-programmable gate arrays (FPGAs). A more detailed analysis of the soft error sensitivity of the 40 nm SRAM-based FPGA was performed. Experimental methods for the configurable logic module, configure memory cells, and block RAM have been introduced for measuring the single event effects (SEEs) induced by alpha particles using a 241Am radiation source. The single event upset (SEU) and single event functional interrupt (SEFI) cross sections of different functional blocks have been calculated to discuss the failure mechanisms of the FPGA. The SEEs test results for the FPGA device based on the 40 nm CMOS process are significant.

A sliced architecture using novel configurable logic modules in quantum dot cellular automata for application of field-programmable gate arrays

A sliced architecture using novel configurable logic modules in quantum dot cellular automata for application of field-programmable gate arrays

Ultra compact pulse shrinking TDC on FPGA

This study propose a new design of a field-programmable gate array (FPGA) based pulse shrinking time-to-digital converter (TDC), where only several configuration logic block (CLB) slices are required to achieve a resolution of around 2.38 ps. Taking advantage of the flip-flop’s asynchronous reset function, along with the characteristics of multiplexers, we propose an ultra compact design and a semi-automatic calibration method. Most importantly, a linear continuous response system for FPGA-based TDC implementation is suggested. Experiments using the Zynq Ultrascale + platform has demonstrated an on-chip resolution of 2.38 ps, DNL = [−0.23; 0.22], and INL = [−0.24; 0.27]. Further, we conducted and analyzed external measurements as well. The measurement range dropped from 210 ps to 80 ps as a result of precision degradation, while the resolution and non-linearity performance remain. This study will discuss the propagation delay, decoupling principle, the semi-auto calibration method, offset introduction, and temperature effects along with several delay tuning techniques.

Design and Implementation of SRAM for LUT and CLB Using Clocking Mechanism in Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA) has long been deemed to be an alternative or supplementary to complementary metal oxide semiconductor (CMOS) technology in theory in the future. In general, QCA works indispensably through a four-phase clocking mechanism. However, previous works on QCA circuits mainly use the clocking to enable the synchronization of signals. In this brief, a static random access memory (SRAM) is proposed for the first time by making use of the phase difference between adjacent clock zones of the unique clocking mechanism. The SRAM saves the address decoders and thus reduces the hardware cost. A look-up table (LUT) is then built through the SRAM to achieve a significant reduction in hardware cost. To verify the practicability of these circuits proposed above, a configurable logic block (CLB) in Xilinx’s XC4000 field-programmable gate array as an example is designed. Simulation results using QCADesigner-E show that the proposed circuits have correct functions and advantages in area, cell count, delay, cost, and energy dissipation compared with previous designs. Note that these circuits are easy to be extended to 16-bit, 32-bit, or higher bit.

Pass-Transistor Logic Circuits Based on Wafer-Scale 2D Semiconductors.

2D semiconductors, such as molybdenum disulfide (MoS2 ), have attracted tremendous attention in constructing advanced monolithic integrated circuits (ICs) for future flexible and energy-efficient electronics. However, the development of large-scale ICs based on 2D materials is still in its early stage, mainly due to the non-uniformity of the individual devices and little investigation of device and circuit-level optimization. Herein, a 4-inch high-quality monolayer MoS2 film is successfully synthesized, which is then used to fabricate top-gated (TG) MoS2 field-effect transistors with wafer-scale uniformity. Some basic circuits such as static random access memory and ring oscillators are examined. A pass-transistor logic configuration based on pseudo-NMOS is then employed to design more complex MoS2 logic circuits, which are successfully fabricated with proper logic functions tested. These preliminary integration efforts show the promising potential of wafer-scale 2D semiconductors for application in complex ICs.

An empirical characterization of software bugs in open-source Cyber–Physical Systems

Background:Cyber-Physical Systems (CPSs) are systems in which software and hardware components interact with each other. Understanding the specific nature and root cause of CPS bugs would help to design better verification and validation (V&V) techniques for these systems such as domain-specific mutants. Aim:We look at CPS bugs from an open-source perspective, trying to understand what kinds of bugs occur in a set of open-source CPSs belonging to different domains. Method:We analyze 1151 issues from 14 projects related to drones, automotive, robotics, and Arduino. We apply a hybrid card-sorting procedure to create a taxonomy of CPS bugs, by extending a previously proposed taxonomy specific to the automotive domain. Results:We provide a taxonomy featuring 22 root causes, grouped into eight high-level categories. Our qualitative and quantitative analyses suggest that 33.4% of the analyzed bugs occurring in CPSs are peculiar to those and, consequently, require specific care during verification and validation activities. Conclusion:The taxonomy provides an overview of the root causes related to bugs found in open-source CPSs belonging to different domains. Such root causes are related to different components of a CPS, including hardware, interface, configuration, network, data, and application logic.

A Lightweight FPGA Compatible Weak-PUF Primitive Based on XOR Gates

In this brief we introduce a novel lightweight FPGA compatible Physical Unclonable Function (PUF) primitive based on XOR gates. The proposed XOR-PUF is the most compact FPGA-compatible PUF ever presented in the literature, allowing the implementation of four PUF bits in a single Configurable Logic Block (CLB) and providing very good statistical performance. The architecture of the proposed PUF exploits two cross-coupled XOR gates which can be configured to behave as ring oscillators or SRAM cells. A 128-bit weak-PUF block based on the proposed XOR-PUF basic cell has been implemented on Xilinx Spartan-6 and Artix-7 devices and an extensive measurement campaign on 16 FPGA devices for each family has been carried out. Measurement results have shown that the proposed architecture and implementation are able to fit in just 64 Slices (32 CLBs) on both the Spartan-6 and Artix-7 devices without sacrificing statistical performance and guaranteeing a good robustness against supply voltage variations.

Object-oriented logic configuration platform design for large power grid security and stability simulation

In response to the multi-state simulation business process requirements of large power grids in actual engineering, a logic configuration platform of large power grid security and stability simulation is designed in this paper. In order to improve the application adaptability of the existing configuration software, firstly, the overall architecture and visual operation interface design of the logic configuration platform of large power grid security and stability simulation are proposed. Secondly, the key technologies to realize the generalized logic configuration platform of large power grid simulation are deeply discussed from the aspects of logic compilation and engine implementation. Thirdly, based on the configuration platform, the innovative application of intelligent large power grid operation mode arrangement system is realized. Practice shows that after the introduction of logic configuration, the time consumption is reduced by more than 85% compared with the traditional manual flow coding method and by more than 90% compared with the traditional manual batch power flow calculation and modulation process, which effectively improves the work efficiency and greatly saves the working time. In the system development, the visual logic configuration mode replaces the engineering customization mode of conventional manual software coding, which greatly improves the engineering adaptability of multi-state large power grid simulation business requirements.

Spin-Orbit Torque Neuromorphic Fabrics for Low-Leakage Reconfigurable In-Memory Computation

In this article, a neural spin-orbit torque (NSOT)-based emerging device technology reconfigurable fabric is developed and assessed as a low-leakage power alternative to the use of a static random access memory (SRAM)-based lookup table (LUT). While other recent designs have explored utilizing spintronic devices as a digital memory cell to replace SRAM-based configuration memory in field programmable gate arrays (FPGAs), the NSOT-LUT fabric exploits small, modularized, and validated artificial neural networks (ANNs) together with the behavior intrinsic of spintronic devices to directly implement novel configuration memory and logic realizations wholly within each LUT. Herein, the NSOT-LUT approach is evaluated within an island-style reconfigurable fabric and then optimized for energy-sparing operation, throughput, and routability. Realization in 45-nm technology is modeled with the Berkeley predictive technology model (BPTM) for CMOS devices and interconnects. Results indicate that the proposed NSOT-LUT fabric can achieve approximately sixfold area savings, twofold speedup, and twofold power savings for a set of 12 benchmark circuits, when compared to an island-style baseline FPGA using spintronic configuration memory.

An adaptive fuzzy PID controller for speed control of brushless direct current motor

Aiming at the problems of the poor adaptive ability in the current control methods for brushless DC motor, an adaptive fuzzy proportional integral derivative controller (AFPID) is proposed to realize the better control performance of speed for brushless DC motor. AFPID includes a conventional PID controller (C-PID) and PI + PD architectures with a configurable fuzzy logic controller (C-PID-FLC). The FLC in C-PID-FLC consists of two fuzzy inference engines, one is used to self-tune the parameters for PI control, the other is for the scaling factor self-tuning of PI control parameters. The PD structure in C-PID-FLC is mainly to reduce oscillation, overcome overshoot and speed up system response while effectively eliminating static errors. When the system reaches a certain stable state of rotation, AFPID adjusts the C-PID controller ground on the speed error, which saves control costs under the premise of ensuring control performance. AFPID adaptively realizes the respective advantages of C-PID and C-PID-FLC. Compared with other control methods, the merits of the proposed controller are highlighted. The results show that the AFPID controller has a better control performance regardless of changes in load disturbance and parameter variations. And through the change of mechanical parameters of brushless DC motor, the sensitivity of AFPID is analyzed.

Implementation of Efficient XOR Arbiter PUF on FPGA With Enhanced Uniqueness and Security

Physically unclonable functions (PUFs) are recently utilized as a promising security solution for authentication and identification of internet of things (IoT) devices. In this article, we present an efficient implementation of XOR Arbiter PUF (XOR APUF) on field-programmable gate arrays (FPGAs). In our work, we incorporated concept of discrete programmable delays logic (PDL) configurations, the obfuscated challenges and temporal majority voting (TMV) before the XOR operation concurrently to enhance uniqueness and security. The derived design has been verified on 25 Xilinx Artix-7 FPGAs and the results are promising with uniqueness of 48.69%, uniformity 50.73% and reliability 99.41%, which significantly improves over previous work into XOR APUF designs. In addition, we also investigate modeling attack resistance of the proposed design against various modelling attacks and the security analysis show that the proposed PUF has lower prediction rate (<65%) when compared to the previous XOR APUF designs.

An Approach to Progress Monitoring of Industrial Manual Processes Based on Camera Recordings and Object Interactions

Despite digitalization and automation, manual processes in factory operations still play a significant role. With the increasing complexity of tasks, it is advisable to support the employee during execution. Technological progress regarding the analysis of image data facilitates the use of camera-based systems for assistance functions. A core element for these assistance systems is the recognition of state or actions to achieve context-sensitive support.However, existing solutions are often developed for specific problems and are difficult to transfer to other processes. This is especially the case for manual processes with more and different sub-process steps such as setup and maintenance operations. High development effort even in case of minor process changes is the result. Therefore, the objective of this work is to develop a generic approach for progress monitoring of manual processes.The proposed approach is based on the understanding that manual processes can be considered as the manipulation of objects to achieve a defined state of their characteristic properties. Consequently, manual processes can be described by their features, like the positions or movements of objects or their relative position to each other. To realize a configurable approach a two-step procedure is proposed. The basis is the flexible recognition and localization of objects in camera recordings by machine learning methods. Subsequently, the information obtained can be utilized by a configurable logic to verify defined states.To develop the detailed concept, firstly, a method for analysis of complex manual processes in factory operation is conducted. The aim is to determine and categorize the objects relevant for optical recognition and state verification. Secondly, different machine learning approaches for object recognition and object localization are compared to evaluate their capability in capturing the feature states. The possible outputs of the machine learning approaches are used to create control elements for progress verification. Examples are the position of objects in relation to each other or the speed of movement. In the next step, a procedure for the process-specific selection of the control elements is developed. Finally, the approach is applied and discussed. A setup process of a turning machine and a deburring process serve as representative use cases.