BIST-based Testing and Diagnosis of LUTs in SRAM-based FPGAs

Hadi Jahanirad,Hanieh Karam

doi:10.28991/ijse-01125

Abstract

FPGA chips have wide applications in nowadays digital systems. Because of fault prone nature of FPGA chips, testing of them is one of the major challenges for designers. Among various test methods, the Built-in Self-Test (BIST) based ones have shown good performance. In this paper, we presented a BIST-based approach to test LUTs as most vulnerable part of FPGA chip. The BIST-based approach is off-line and has been accomplished within two FPGA configurations. Each configurable logic block (CLB) can be tested independently and there is no handshaking among various CLBs' BIST cores. The proposed BIST architecture has been simulated in HSPICE based on 45-nm CMOS technology. Simulation results shown 100% coverage for single stuck at faults along with 19% area overhead due to additional BIST hardware and 25% increase in leakage power.

Highlights

FPGA (Field Programmable Gate Array) chips have become an important part in modern digital systems
Using Built-in Self-Test (BIST) technique in circuit test has more advantages compared to normal counterpart
Automatic test equipment ATE for constructing normal test in conventional VLSI circuits includes hardware test using expensive hardware and long solution

Summary

1- Introduction

FPGA (Field Programmable Gate Array) chips have become an important part in modern digital systems. In-field re-configurability of these chips has shortened the time to market for most applications. Various test approaches for FPGA chips have been developed in recent decades. BIST as a testing method for logic circuits has been widely used [3,4,5,6]. In last two decades different BIST architectures have been developed for FPGA testing; each of them has some pros and cons [7,8,9]. Various methods have been proposed to test CLB These methods are different in test time and the number of required CLB configurations. BIST as an efficient testing method is based on constructing a hardware core in CMOS-chip to make the testing operation internally [10].

1-1- Related Works

3- Simulation Results

4- Conclusion

5- References