Configurable Logic Research Articles

Configurable Logic Blocks and Memory Blocks for Beyond-CMOS FPGA-Based Embedded Systems

Field programmable gate arrays (FPGAs)-based embedded systems are easy to implement, reconfigure, test, and validate. Configurable logic blocks (CLBs) and memory blocks are the building blocks of FPGA. The rising issues in CMOS fabrication at smaller nanometer levels has increased the need for beyond-CMOS technologies to build complex circuits at extremely smaller nanometer levels. Quantum-dot cellular automata (QCA) is a nascent beyond-CMOS nanotechnology technique to design low-power and high-performance digital circuits. In this letter, a layout strategy is proposed to design QCA circuits. Using the proposed strategy, novel and cost-efficient designs of CLBs and memory blocks are proposed. The proposed blocks can be used to develop FPGA architecture and FPGA-based embedded systems in QCA. The proposed circuits are cost effective and perform better than many state-of-the-art designs. Simulation and verification are done in QCADesigner using coherence vector simulation engine.

All-Graphene Nano-Ribbon FET Based Complete FPGA Design

FPGA is among the most successful digital IC. Though initially targeted for prototyping, but received more attention even in small volume production. However, that success is under threat since Silicon is reaching physical limitations. According to ITRS, towards the sub-nanometer regime, various second-order effects affect the functionality and reduces the performance of the device. Research on alternative materials indicates that Graphene is the most attractive candidate, and field-effect transistors using Graphene Nano-Ribbons Field Effect Transistors (GNRFETs) are promising because of their excellent properties. Toward all-Graphene microelectronics, and due to FPGA position in digital design, Graphene-based FPGA needs to be designed, analyzed, and evaluated. This paper explores FPGA design based on GNRFETs. It studies the design and characterization of all parts of a Graphene-based simple FPGA which could be a configurable logic structure for future microelectronics. It covers main parts, by design and characterization of Configurable Logic Block, routing switch, and I/O block, all based on GNRFET. The results as 47 ps delay for output and 23 ps for input proves feasibility, and indicate that proposed C-FPGA designs are much faster than conventional silicon-based counterparts. Power Delay Product of proposed CLB element is 5.3 times lesser than those of silicon counterparts.

Political Ontogenesis: (Through) Affects (Towards) Becoming (And) Immanent Critique

Political Ontogenesis(Through) Affects (Towards) Becoming (And) Immanent Critique Denis Petrina The statement that ontology has been at the very core of philosophy may seem a truism. Even more so when we consider that Aristotle granted ontology the status of "first philosophy" (58/149), which means that the latter should concern itself primarily with the study of being—haplos—as a very peculiar form of being: being as being or being in itself. This set a course for the subsequent development of philosophical thought: since ancient times, philosophers have mainly been preoccupied with the "distillation" of being, the removal of its intrinsic antinomies, id est, the purification of being. In this paper, I attempt to diverge from this established route and question this unquestionable philosophical ambition to speak of ontology as a singular and universal theory of being. When reading Aristotle, Sergei Prozorov insightfully notes that the equation "ontology = first philosophy" disguises a not so readily apparent unsettling commonality between ontology and what he terms "political anthropology" (Prozorov, World 105), or what we may call ideology. Interestingly, idea is an invisible yet strong link that ties philosophy and ideology together. Plato, the first post-Socratic philosopher, placed idea—an idea(l) form, contraposed with imperfect materiality—at the heart of his philosophical system. Viewed from this perspective, the idea component in ideology can be described as an underlying form that shapes, unites, and holds its components together. Thus, translated into philosophical terms, ideology is nothing but (an) ontology. This brief genealogical inquiry allows us to acquire a different viewpoint, from which we can look at ontology in at least two ways. On the one hand, ontology qua ideology (and vice versa) presupposes the contextual and subjective nature of ontology: ontology is always a correlative of the subject, or, placed in a political context, of a group of subjects. On the other hand, politics is elevated to ontological status, which results in the legitimation of a certain political context, of the interests of a certain group of subjects, and thus, ultimately, of a certain sociopolitical status quo. Even at this stage, the attempt to conceptualize [End Page 83] ontology as pure, devoid of any supplements being, appears as a highly ideological enterprise that remains (or at least pretends to be) unaware of its own political implications. This relation is symmetric: ontology is as much politically oriented as politics is oriented ontologically. "What is being?"—a seemingly philosophical question ontology raises might be easily translated into a normative one, that is: "What ought being to be?". If this question is perceived as pertaining to life, the normative question might easily become biopolitical: "What ought being not to be?". Thus, ontology, allied with politics, reveals itself as an inherently political apparatus that, in a classical biopolitical manner, governs being—however, not at its material level, as it occurs in the field of politics—but, instead at a conceptual-perceptual level. Here, we should take the descriptor "conceptual" in all its seriousness. Even though the conceptual framing is immaterial, its power is material, or, even more precisely, more than material. As Gilles Deleuze and Félix Guattari argue, not only is any concept composed of a variety of heterogeneous (both material and immaterial) components—but, more importantly, it has a totalizing power over its components too (Deleuze, Guattari, Philosophy 15–16). In a similar vein, Michel Foucault maintains that a contemporary neoliberal regime is characterized by its alarmingly biopolitical goal of governing both individuals and populations (Foucault, Sexuality 141) through both material and discursive, or conceptual, means. To phrase it metaphorically, this resembles a game of mirrors: ontology reflects politics—and politics reflects ontology. Brian Massumi, reacting to this alarming symptom of the neoliberal regime, has coined the term "ontopower," a portmanteau combining "ontology" and "power." Massumi maintains that ontopower has a dual aim: not only does it endeavor to administer being, but it also controls and governs opportunities of it (Massumi, Ontopower vii). The next chapter will explore this new configuration, topology, and operative logic of power in more detail. ontopower (i): biopower The starting point for Massumi's conceptual operationalization of ontopower is Foucault's theoretical framing of the neoliberal or, alternatively...

Toward Secured FPGA: Silicon Proven CLB With Reduced Information Leakage

The ubiquity of FPGAs in security applications makes it imperative to design a secured configurable logic block (sCLB) that is resilient to side channel attacks. In this letter, we take a step toward secured FPGA by introducing new design circuit level methodology for the implementation of an sCLB. The security level of the sCLB is significantly enhanced by the design of its combinational part (LUT block) based on a dual-rail precharge MUX (DPMUX). The sCLB was implemented in a configurable array and fabricated in 65-nm CMOS technology. Silicon measurements proved the effectiveness of the approach. The security level was evaluated using advanced power analysis techniques. In particular, the number of secret bits that can be learned (mutual information) by a CPA attack dropped from 4 b (out of 4) after 1200 power traces for a conventional LUT design to only 2.56 b after 19.2-M power traces.

Colorimetric chiral discrimination of lysine enantiomers and configurable logic gate operation based on fluorescein-functionalized polydiacetylene vesicles

This study describes a sensitive sensor for based on fluorescein-functionalized diacetylene (F-DA) chromatic conjugated vesicle which allows colorimetric visualization for the chiral recognition of lysine by the naked-eye.

Technique to Dynamically Reconfigure FPGAs using Control Registers

Due to increased use of FPGAs computation intensive applications, the need for embedded processing system integrated with programmable logic device has also increased. Configuration of programmable logic device by the processing system through its interface improves the efficiency of the device. In order to operate as a stand-alone device and to have a better efficiency, the programmable logic device must be capable of dynamically programming its own configuration memory. In this paper, we propose a configurable logic block with a control register to improve performance of the programmable logic device. The control register acts like a decentralized configuration memory array which can be programmed by other such configurable logic blocks. The FPGAs are fault tolerant devices with repetitive structures requiring high packaging density. This property of FPGA enables the use of CNTFETs for design of FPGAs. CNTFETs offer high trans-conductance and 1-D ballistic transport of electrons and holes which minimizes the power consumed by the FPGA. The proposed control register based architecture was implemented using Cadence Virtuoso using virtual source CNTFET model from Stanford University. A power reduction of 17.62% is achieved using CNTFETs when compared with FINFET at same technology node and the architecture was verified for various configurations of the control register.

MRAM-Enhanced Low Power Reconfigurable Fabric With Multi-Level Variation Tolerance

A hybrid device technology reconfigurable logic fabric is proposed which leverages the cooperating advantages of distinct magnetic random access memory (MRAM)-based look-up tables (LUTs) to realize sequential logic circuits, along with conventional SRAM-based LUTs to realize combinational logic paths. A hierarchical top-down design approach is used to develop a hybrid spin/charge based FPGA (HSC-FPGA) starting from the configurable logic block (CLB) and slice structures down to LUT circuits and the corresponding device fabrication challenges. Circuit-level simulations indicate at least 40% and 83% read and standby power reduction, respectively, for MRAM-LUTs compared to SRAM-LUTs. However, MRAM-LUTs using spin transfer torque (STT) switching approach suffers from significant write energy consumption. Therefore, we have designed spin Hall effect (SHE)-assisted MRAM-LUTs realizing more than 67% and 61% reduction in reconfiguration energy and area consumption, respectively. Fabric-level simulations exhibit that HSC-FPGA achieves 70% and 30% reductions in standby and read power, respectively, compared to SRAM-based FPGAs for various ISCAS-89 and ITC-99 benchmark circuits. Finally, a multi-level method spanning device-sizing, circuit modular-redundancy, and component-level reconfiguration is developed to increase the process variation resiliency of the MRAM-LUTs. The power consumption and area utilization are analyzed to formulate tradeoffs resulting in recommendations toward future multi-device-based reconfigurable fabrics.

Design of Low Power CMOS Array and Tree Multiplier using DSM Technology

currently days, improvement of digital gadgets has been advanced. The requirement for low-manage configuration is additionally turning into a noteworthy problem in superior computerized framework plan programs. A 4 piece CMOS Multiplier has one heart of the chip in dealing with framework structure it require low manipulate usage This paper complicated the multiplier plans of both Array and Tree in 90nm, 65nm, improvements. on this the real segment is CMOS multiplier in labored of adders which makes use of conventional Static CMOS (CSL) logic configuration fashion using the Deep Submicron innovation at various stock voltages. the key point of our mission is to consider the CMOS Array and Tree 4x4 Multipliers concerning Propagation delay, strength dissemination and Transistor check. the usage of CMOS 1 piece complete snake cell for low power is won and is actualized on Array and Tree multiplier and the consequences are investigated for stepped forward strength delay item. The circuit plan and reenactment is finished with MICROWIND tool

A New Paradigm for FPGA Placement Without Explicit Packing

Placement and packing are two important but separated optimization steps in a conventional field programmable gate array (FPGA) implementation flow. A packing engine clusters logic elements, like lookup tables and flip-flops, into configurable logic blocks, while a placement engine determines their physical locations in FPGA layouts. This paper presents a new paradigm for FPGA placement without an explicit packing stage. In the proposed framework, the solution spaces of placement and packing are simultaneously explored in a smooth and elegant way. Our experiments on ISPD 2016 and 2017 benchmark suites demonstrate the effectiveness of the proposed framework.

Realization of Sequential Control Function Based on Bay Level Equipment in Smart Substation

In view of the problem of low reliability and automation of advanced application functions such as sequential control in smart substation, the logic configuration mode of sequential control is analyzed based on the principle of logic virtual circuit of bay level equipment in smart substation, and the realization of sequential control function based on bay level equipment is proposed. This method improves the operational reliability and configuration flexibility of sequential control, and fundamentally solves the technical application problem, so as to improve the intelligent level of power grid.

Design of Hybrid LUT/MUX FPGA Logic Architecture for size Reduction and Performance Improvement in FPGA

Hybrid configurable logic block architectures for field-programmable gate arrays that contain a blend of LUT's and solidified multiplexers that are assessed towards the objective of higher rationale thickness and diminished region. Innovation mapping advancements that focus on the proposed models are likewise perform inside Xilinx programming. Both for complex rationale square and steering territory while keeping up mapping profundity, the named engineering of this paper examine the rationale size, region and power utilization utilizing Xilinx 14.5.

Hardware Optimizations of Dense Binary Hyperdimensional Computing: Rematerialization of Hypervectors, Binarized Bundling, and Combinational Associative Memory

Brain-inspired hyperdimensional (HD) computing models neural activity patterns of the very size of the brain’s circuits with points of a hyperdimensional space, that is, with hypervectors . Hypervectors are D -dimensional (pseudo)random vectors with independent and identically distributed (i.i.d.) components constituting ultra-wide holographic words: D =10,000 bits, for instance. At its very core, HD computing manipulates a set of seed hypervectors to build composite hypervectors representing objects of interest. It demands memory optimizations with simple operations for an efficient hardware realization. In this article, we propose hardware techniques for optimizations of HD computing, in a synthesizable open-source VHDL library, to enable co-located implementation of both learning and classification tasks on only a small portion of Xilinx UltraScale FPGAs: (1) We propose simple logical operations to rematerialize the hypervectors on the fly rather than loading them from memory. These operations massively reduce the memory footprint by directly computing the composite hypervectors whose individual seed hypervectors do not need to be stored in memory. (2) Bundling a series of hypervectors over time requires a multibit counter per every hypervector component. We instead propose a binarized back-to-back bundling without requiring any counters. This truly enables on-chip learning with minimal resources as every hypervector component remains binary over the course of training to avoid otherwise multibit components. (3) For every classification event, an associative memory is in charge of finding the closest match between a set of learned hypervectors and a query hypervector by using a distance metric. This operator is proportional to hypervector dimension ( D ), and hence may take O( D ) cycles per classification event. Accordingly, we significantly improve the throughput of classification by proposing associative memories that steadily reduce the latency of classification to the extreme of a single cycle. (4) We perform a design space exploration incorporating the proposed techniques on FPGAs for a wearable biosignal processing application as a case study. Our techniques achieve up to 2.39× area saving, or 2,337× throughput improvement. The Pareto optimal HD architecture is mapped on only 18,340 configurable logic blocks (CLBs) to learn and classify five hand gestures using four electromyography sensors.

Socioeconomic Factors, Income Transfer Program, and the Presidential Election of 2014: Regional Voting Patterns in Brazil

An academic debate underway has sought to understand geographical polarization in the Brazilian presidential election. Recent studies have analyzed the additive effects on regional voting behavior from an economic, social, and institutional perspective, sometimes including the income transfer program Bolsa Família. However, these dimensions potentially form multiple distinct configurations that lead to a high or low voting result (percentage). The aim of this paper is to identify these logical combinations and analyze them to shed light on the regional patterns that are most consistent with the in the 2014 presidential election. The main findings suggest that the logical combination of a high percentage of Bolsa Família beneficiaries and a low degree of economic development or unfavorable domicile, urban, and social conditions covers 83% of the cases. This regional pattern of logic configurations was consistent with the pattern of voting based on political party.

Una fundamentación universalita de los derechos humanos

El artículo pretende establecer el contexto teórico general para propiciar una discusión en torno a la apremiante tarea de fundamentar los derechos humanos desde un criterio universalista. Se intentará proveer a los derechos humanos de una justificación teórica universal más allá de la que contiene su simple enunciación como derechos universales. Se recurre a la filosofía normativa kantiana, que es un paradigma del análisis de los enunciados con contenido normativo, para acometer el propósito de dotar a los derechos humanos de una fundamentación propiamente normativa, es decir, en su contenido intrínseco como normas. Una fundamentación en sentido universalista es aquella que tiene su fuerza vinculante en el contenido de la norma en sí misma, en su estructura lógica.

A voltage-mode RF DAC for massive MIMO system-on-chip digital transmitters

As the number of antenna elements increases in massive multiple-input multiple-output-based radios such as fifth generation mobile technology (5G), designing true multi-band base-station transmitter, with efficient physical size, power consumption and cost in emerging cellular frequency bands up to 10 GHz, is becoming a challenge. This demands a hard integration of radio components, particularly the radio’s digital application-specific integrated circuits (ASIC) with high performance multi-band data converters. In this work, a novel radio frequency digital-to-analog converter (RF DAC) solution is presented, that is also capable of monolithic integration into today’s digital ASIC due to its digital-in-nature architecture. A voltage-mode conversion method is used as output stage, and configurable mixing logic is employed in the data path to create a higher frequency lobe and utilize the output signal in the first or the second Nyquist zone. This 12-bit RF DAC is designed in a 22 nm FDSOI CMOS process, and shows excellent linearity performance for output frequencies up to 10 GHz, with no calibration and no trimming techniques. The achieved linearity performance is able to fulfill the high requirements of 5G base-station transmitters. Extensive Monte-Carlo analysis is performed to demonstrate the performance reliability over mismatch and process variation in the chosen technology.

Implementation of Low Power Null Conventional Logic Function for Configuration Logic Block

Todays, transistor level design plays major impact in the power consumption of the VLSI based design. The various logic design models are used to reduce the power consumption that includes synchronous and asynchronous design model. The operation of synchronous circuit is limited by the in phase factor of the clock pulse signal which is used to control the synchronous circuit. In contrast, asynchronous circuits are used widely because it causes low noise, require less power. It affects the less electromagnetic interference that allows reuse of the components. These asynchronous circuits are being implemented by Null Conventional Logic (NCL) which is a delay insensitive logic model. The Configuration Logic Block is the power consuming model in Field Programmable Gate Array (FPGA). This block contains the lookup table (LUT) and 27 fundamental NCL logic gates. To reduce the power consumption of this module, we use the Differential Cascade Voltage Switch Logic (DVSL). The power reduction is achieved in LUT by means of DVSL and minimizes the number transistors. This NCL, DVSL, FPGA logic element is simulated using 90 nm TSMC CMOS processing technology.

A true random number generator architecture based on a reduced number of FPGA primitives

This paper reports on the design, realization and characterization of a True Random Number Generator (TRNG) that operates using as seeds of entropy, the jitter and the metastability introduced by primitives of a Field Programmable Gate Arrays (FPGA) board. In particular, the TRNG architecture has been implemented on a Xilinx Ultrascale XCKU040 FPGA board. Generally, the implementations on FPGA of fully-digital TRNGs make use of ring oscillators employing a large number of Look-Up-Table (LUT) blocks. Differently from this approach, this paper demonstrates that a reliable FPGA-based TRNG architecture can be realized mainly employing only a single PLL and three on-board primitives together with other few basic logic elements (i.e., 8 D-type Flip-Flop, 17 LUT and 2 Counters) used only for the initial overall system synchronization and post-processing operations. In this way, the proposed solution largely reduces the employed number of the FPGA Configurable Logic Blocks (CLB), the circuitry complexity and the overall power consumption without affecting the achievable output bit rate so resulting suitable for full-custom VLSI implementations. The random and statistical properties of the generated 100 Mbps output bitstreams have been validated by passing all the National Institute of Standards and Technology (NIST) tests as well as the Anderson-Darling and the Kolmogorov-Smirnov tests so demonstrating that the proposed TRNG architecture can be suitably employed in security/cybersecurity network systems as well as, once integrated, in Internet-of-Things (IoT) and Industrial-Internet-of-Things (IIoT) applications.

Multidimensional characteristics and deforestation: an analysis for the Brazilian Legal Amazon

The current debate concerning the Legal Amazon in Brazil suggests that deforestation is a multidimensional phenomenon. Many studies have analysed deforestation in this region in the economic and institutional spheres, treating them jointly or separately. However, in addition to including family structure and social aspects, this work seeks to identify the multiple configurations that potentially lead to deforestation. We applied exploratory statistical techniques to analyse the 762 municipalities located in the Legal Amazon and to extract four characteristic dimensions, namely, economic development, family labour farming, property and rural density and openness to trade. One of the main results suggests the logical configuration between high economic development and the number of establishments occupied by squatters, with high rural populations covering 54% of the municipalities analysed, which is highly consistent (84%) with the high deforestation in the Legal Amazon.

An Efficient SRAM-Based Reconfigurable Architecture for Embedded Processors

Nowadays, embedded processors are widely used in wide range of domains from low-power to safety-critical applications. By providing prominent features such as variant peripheral support and flexibility to partial or major design modifications, field-programmable gate arrays (FPGAs) are commonly used to implement either an entire embedded system or a hardware description language-based processor, known as soft-core processor. FPGA-based designs, however, suffer from high power consumption, large die area, and low performance that hinders common use of soft-core processors in low-power embedded systems. In this paper, we present an efficient reconfigurable architecture to implement soft-core embedded processors in SRAM-based FPGAs by using characteristics such as low utilization and fragmented accessibility of comprising units. To this end, we integrate the low utilized functional units into efficiently designed look-up table (LUT)-based reconfigurable units (RUs). To further improve the efficiency of the proposed architecture, we used a set of efficient configurable hard logics that implement frequent Boolean functions while the other functions will still be employed by LUTs. We have evaluated effectiveness of the proposed architecture by implementing the Berkeley RISC-V processor and running MiBench benchmarks. We have also examined the applicability of the proposed architecture on an alternative open-source processor (i.e., LEON2) and a digital signal processing core. Experimental results show that the proposed architecture as compared to the conventional LUT-based soft-core processors improves area footprint, static power, energy consumption, and total execution time by 30.7%, 32.5%, 36.9%, and 6.3%, respectively.

Multi‐objective optimisation algorithm for routability and timing driven circuit clustering on FPGAs

Circuit clustering algorithms fit synthesised circuits into field programmable gate array (FPGA) configurable logic blocks (CLBs) efficiently. This fundamental process in FPGA CAD flow directly impacts both effort required and performance achievable in subsequent place-and-route processes. Circuit clustering is limited by hardware constraints of specific target architectures. Hence, better circuit clustering approaches are essential for improving device utilisation whilst at the same time optimising circuit performance parameters such as, e.g. power and delay. In this study, the authors present a method based on multi-objective genetic algorithm (MOGA) to facilitate circuit clustering. They address a number of challenges including CLB input bandwidth constraints, improvement of CLB utilisation, minimisation of interconnects between CLBs. The authors’ new approach has been validated using the ‘Golden 20’ MCNC benchmark circuits that are regularly used in FPGA-related literature. The results show that the method proposed in this study achieves improvements of up to 50% in clustering, routability and timing when compared to state-of-the-art approaches including VPack, T-VPack, RPack, DPack, HDPack, MOPack and iRAC. The key contribution of this work is a flexible EDA flow that can incorporate numerous objectives required to successfully tackle real-world circuit design on FPGA, providing device utilisation at increased design performance.