Configurable Logic Blocks Research Articles

Aging Resilience and Fault Tolerance in Runtime Reconfigurable Architectures

Runtime reconfigurable architectures based on Field-Programmable Gate Arrays (FPGAs) allow areaand power-efficient acceleration of complex applications. However, being manufactured in latest semiconductor process technologies, FPGAs are increasingly prone to aging effects, which reduce the reliability and lifetime of such systems. Aging mitigation and fault tolerance techniques for the reconfigurable fabric become essential to realize dependable reconfigurable architectures. This article presents an accelerator diversification method that creates multiple configurations for runtime reconfigurable accelerators that are diversified in their usage of Configurable Logic Blocks (CLBs). In particular, it creates a minimal number of configurations such that all single-CLB and some multi-CLB faults can be tolerated. For each fault we ensure that there is at least one configuration that does not use that CLB. Second, a novel runtime accelerator placement algorithm is presented that exploits the diversity in resource usage of these configurations to balance the stress imposed by executions of the accelerators on the reconfigurable fabric. By tracking the stress due to accelerator usage at runtime, the stress is balanced both within a reconfigurable region as well as over all reconfigurable regions of the system. The accelerator placement algorithm also considers faulty CLBs in the regions and selects the appropriate configuration such that the system maintains a high performance in presence of multiple permanent faults. Experimental results demonstrate that our methods deliver up to 3.7× higher performance in presence of faults at marginal runtime costs and 1.6× higher MTTF than state-ofthe-art aging mitigation methods.

A Hybrid Logic Block Architecture in FPGA for Holistic Efficiency

This brief presents a hybrid design of a configurable logic block (CLB) composed of look-up tables (LUTs) and universal logic gates (ULGs). A ULG is designed to realize holistic efficiency compared with the corresponding LUT. Previous designs with ULGs are either based on pure ULG or LUT-ULG complementary architecture, which incur a longer delay or double the area compared to the LUT-based design. In contrast, we propose a hybrid CLB that contains a mixture of LUTs and ULGs to address the generality problem as well as to achieve the holistic benefits including the area, performance, and power. To exploit the advantage of ULGs thoroughly while not causing negative side effects, the ratio of LUTs and ULGs in one CLB is explored by experiments. Experimental results show that, compared to pure LUT design, our proposed architecture design can save up to 17.1% logic power as well as 11.2% delay improvement and 10.4% logic area reduction. Compared to the state-of-the-art design, our proposed design has 3.8% improvement in power delay product and 17.1% improvement in area cost.

ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware

Field programmable gate arrays (FPGAs) are well-established as fine-grained reconfigurable computing platforms. However, FPGAs demonstrate poor scalability in advanced technology nodes due to the large negative impact of the elaborate programmable interconnects (PIs). The need for such vast PIs arises from two key factors: 1) fine-grained bit-level data manipulation in the configurable logic blocks and 2) the purely spatial computing model followed in the FPGAs. In this paper, we propose ENFIRE, a novel memory-based spatio-temporal framework designed to provide the flexibility of reconfigurable bit-level information processing while improving scalability and energy efficiency. Dense 2-D memory arrays serve as the main computing elements storing not only the data to be processed but also the functional behavior of the application mapped into lookup tables. Computing elements are spatially distributed, communicating as needed over a hierarchical bus interconnect, while the functions are evaluated temporally inside each computing element. A custom software framework facilitates application mapping to the framework. By leveraging both spatial and temporal computing, ENFIRE significantly reduces the interconnect overhead when compared with FPGA. Simulation results show an improvement of $7.6\times $ in energy, $1.6\times $ in energy efficiency, $1.1\times $ in leakage, and $5.3\times $ in unified energy efficiency, a metric that considers energy and area together, compared with comparable FPGA implementations.

Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing

In modern SRAM based Field Programmable Gate Arrays, a Look-Up Table (LUT) is the principal constituent logic element which can realize every possible Boolean function. However, this flexibility of LUTs comes with a heavy area penalty. A part of this area overhead comes from the increased amount of configuration memory which rises exponentially as the LUT size increases. In this paper, we first present a detailed analysis of a previously proposed FPGA architecture which allows sharing of LUTs memory (SRAM) tables among NPN-equivalent functions, to reduce the area as well as the number of configuration bits. We then propose several methods to improve the existing architecture. A new clustering technique has been proposed which packs NPN-equivalent functions together inside a Configurable Logic Block (CLB). We also make use of a recently proposed high performance Boolean matching algorithm to perform NPN classification. To enhance area savings further, we evaluate the feasibility of more than two LUTs sharing the same SRAM table. Consequently, this work explores the SRAM table sharing approach for a range of LUT sizes (4–7), while varying the cluster sizes (4–16). Experimental results on MCNC benchmark circuits set show an overall area reduction of ~7% while maintaining the same critical path delay.

Highly optimised reconfigurable hardware architecture of 64 bit block ciphers MISTY1 and KASUMI

Highly optimised reconfigurable hardware architecture is proposed of 64 bit block ciphers MISTY1 and KASUMI for wide-area cryptographic applications. The reconfigurable hardware architecture is comprised of reconfigurable components consisting of FL function, FO/FI function and XOR function designed to perform MISTY1 and KASUMI algorithms round transformation functions. In addition, reconfigurable FO/FI function is adequate to generate MISTY1 extended keys for onward use in MISTY1 round transformation function. The substitution functions S9 and S7 for MISTY1 and KASUMI algorithms are optimised for area and throughput. Common sub-expression elimination for AND-XOR logic combined with permutation/combination technique for AND gates reduces the area considerably, whereas parallel execution improves the throughput. With this design approach, application specific integrated circuit (ASIC) implementations using Synopsys Design Complier, SMIC 0.18 µm at 1.8 V achieved an area of 3481 NAND gates having throughput of 130.2 and 154.56 Mbits/s for MISTY1 and KASUMI, respectively. Synthesised FPGA implementation using Xilinx Artix 7 FPGA yielded an area of 487 configurable logic block (CLB) Slices having throughput of 209.43 and 248.7 Mbits/s for MISTY1 and KASUMI, respectively. Detailed design and performance analysis of reconfigurable hardware architecture of 64 bit block ciphers MISTY1 and KASUMI for ASIC implementations is described.

SSTL I/O Based Current Optimized Thermal Energy Efficient ROM Design on 28nm FPGA

In this work, energy efficient ROM is being designed using Kintex 7 which is able to scale down the circuit to 28 nm. For Testing the ROM compatibility, ROM is operated on operating frequencies (10GHz, 15GHz, 20GHz, 25GHz ) .Whenever capacitance is scaled down from 15pf to 5pf, there is I/O power and total power reduction but it is observed that there is no reduction in Clock power, and a very small reduction in leakage power. FPGA is an Integrated Circuit that comprises of input/output buffer, programmable interconnect structure and an array of configurable logic blocks, which featurisms fast prototyping and consumer configurability which gives the advantage of short turnaround time( i.e. time required from start of process till a functional chip is obtained).10MBits of on chip Memory is being provided on Xilinx FPGA in 36Kbits blocks, which supports dual port operation. Stub Series Terminated Logic (SSTL) is an Input/output standard which is selected because it avoids the transmission lie reflection and overall power dissipation. The purpose of Voltage scaling is to reduce leakage power. When capacitance of output load is scaled from 50pF to 5pF, there are 32-37% saving in I/O Power, 0-0.1% Leakage Power saving, there will be a 1-5% saving in Total Power. This design is implemented on Kintex-7 FPGA using Xilinx ISE & Verilog. The technique of Frequency Scaling has been used to reduce the leakage power consumption within the range of 80% to 44.8%, consumption in total power in range of 45.8% to 21.36% and the reduction in Junction temperature range is from 3.5% to 1.6% for 10GHz frequency.

Configurable memristive logic block for memristive-based FPGA architectures

This article proposes a Configurable Memristive Logic Block (CMLB) that comprises of novel memristive logic cells. The memristive logic cells are constructed from memristive D flip-flop, 6-bit non-volatile look-up table (NVLUT), and multiplexers. The memristive logic cells are interconnected using memristive switch matrix cells to form the CMLB. The CMLB is then used to construct a memristor-based FPGA architecture. The proposed CMLB shows a reduction of 8.6% of device area and 1.094 times lesser critical path delay against the SRAM-based FPGA architecture. Against similar CMOS-based circuits, the memristive D flip-flop provides switching speed of 1.08 times faster, the NVLUT reduces power consumption by 6.25nW, and the memristive logic cells reduce device area by 60.416µm2. In this research work also, various memristor-based FPGA architectures found in the literature are compared against the SRAM-based FPGA architecture.

Low-Complexity Image and Video Coding Based on an Approximate Discrete Tchebichef Transform

The usage of linear transformations has great relevance for data decorrelation applications, like image and video compression. In that sense, the discrete Tchebichef transform (DTT) possesses useful coding and decorrelation properties. The DTT transform kernel does not depend on the input data and fast algorithms can be developed to real time applications. However, the DTT fast algorithm presented in literature possess high computational complexity. In this work, we introduce a new low-complexity approximation for the DTT. The fast algorithm of the proposed transform is multiplication-free and requires a reduced number of additions and bit-shifting operations. Image and video compression simulations in popular standards shows good performance of the proposed transform. Regarding hardware resource consumption for FPGA shows 43.1% reduction of configurable logic blocks and ASIC place and route realization shows 57.7% reduction in the area-time figure when compared with the 2-D version of the exact DTT.

Multiple-tapped-delay-line hardware-linearisation technique based on wire load regulation

This article describes designing, implementation and tuning processes of multiple-tapped-delay-line (MTDL). Obtained MTDL can be implemented in various field-programmable-logic-devices (FPGA) devices and applied for time-to-digital-converters (TDC) construction. The task of tuning process is the tapped-delay-line (TDL) linearisation, and consists of two stages. The first stage depends on selecting an appropriate configurable-logic-block (CLB) for particular delay-segment realization and selecting proper connection between these blocks. The second tuning stage, that is essential from this article viewpoint, depends on inter CLBs connecting wires delay regulation realized directly by load regulation. The Load regulation depends on connecting an appropriate number of unused three-state-buffers or CLB inputs to the wire which delay is adjusted. Depending on the number of inputs connected to the wire its capacitance changes that influences its time-constant and finally changes its time-delay. The MTDL mathematical model, obtained characteristics and results of time-interval (TI) measurements are also presented. The derived TDL model provides information about how the particular wire delay should be changed and in which order the changes should be executed. This makes the designing process predictable and easy to carry out. Presented characteristics confirm the proper operation of presented linearisation technique. The proper operation of the whole measuring module is confirmed by obtained TIs histograms presentation.

Hybrid LUT/Multiplexer FPGA Logic Architectures

Hybrid configurable logic block architectures for field-programmable gate arrays that contain a mixture of lookup tables and hardened multiplexers are evaluated toward the goal of higher logic density and area reduction. Multiple hybrid configurable logic block architectures, both nonfracturable and fracturable with varying MUX:LUT logic element ratios are evaluated across two benchmark suites (VTR and CHStone) using a custom tool flow consisting of LegUp-HLS, Odin-II front-end synthesis, ABC logic synthesis and technology mapping, and VPR for packing, placement, routing, and architecture exploration. Technology mapping optimizations that target the proposed architectures are also implemented within ABC. Experimentally, we show that for nonfracturable architectures, without any mapper optimizations, we naturally save up to ~8% area postplace and route; both accounting for complex logic block and routing area while maintaining mapping depth. With architecture-aware technology mapper optimizations in ABC, additional area is saved, post-place-and-route. For fracturable architectures, experiments show that only marginal gains are seen after place-and-route up to ~2%. For both nonfracturable and fracturable architectures, we see minimal impact on timing performance for the architectures with best area-efficiency.

Field Programmable Gate Array Reliability Analysis Using the Dynamic Flowgraph Methodology

Field programmable gate array (FPGA)-based systems are thought to be a practical option to replace certain obsolete instrumentation and control systems in nuclear power plants. An FPGA is a type of integrated circuit, which is programmed after being manufactured. FPGAs have some advantages over other electronic technologies, such as analog circuits, microprocessors, and Programmable Logic Controllers (PLCs), for nuclear instrumentation and control, and safety system applications. However, safety-related issues for FPGA-based systems remain to be verified. Owing to this, modeling FPGA-based systems for safety assessment has now become an important point of research. One potential methodology is the dynamic flowgraph methodology (DFM). It has been used for modeling software/hardware interactions in modern control systems. In this paper, FPGA logic was analyzed using DFM. Four aspects of FPGAs are investigated: the “IEEE 1164 standard,” registers (D flip-flops), configurable logic blocks, and an FPGA-based signal compensator. The ModelSim simulations confirmed that DFM was able to accurately model those four FPGA properties, proving that DFM has the potential to be used in the modeling of FPGA-based systems. Furthermore, advantages of DFM over traditional reliability analysis methods and FPGA simulators are presented, along with a discussion of potential issues with using DFM for FPGA-based system modeling.

Power Optimization of Configurable Logic Block in FPGA via Controlling Logic State of Virtual Ground Voltage

In this article, power optimization is investigated in Configurable Logic Block (CLB) of Field Programmable Gate Array (FPGA) for 65nm technology via controlling Virtual Ground Voltage (Vssv) state that follows Power-Gated standard. Initially different Configurable Logic Block are designed through the logic gates and then expanded via adding Look Up Table circuit (LUT) in inputs; afterwards, the samples of Configurable Logic blocks are investigated in two logic states of Virtual Ground Voltage =0 and Virtual Ground Voltage =1 regarding the power dissipation; whereas 100µs is time reference for simulation of time controller of Virtual Ground Voltage function. First Configurable Logic Block are kept at logic state of Virtual Ground Voltage =1(power gated) for 10µs out of 100µs and remaining time at logic state of Virtual Ground Voltage =0 (power not gated); then the simulation test is repeated up to 50µs in 5 steps for each Configurable Logic Block sample. Finally the result shows that reduction being at logic state of Virtual Ground Voltage =0 in a constant time period has linear effect on decreasing average power. With the Configurable Logic Block in operation for 50% of the total time in Virtual Ground Voltage =1 logic state, the average power reduces up to 49% in the best case scenario. Meanwhile the Configurable Logic Block can still preserve its logic state.

Low Power CMOS Look-Up Tables using PROM

Field Programmable Gate Array (FPGA) based designs are the most popular trend towards semiconductor technology evolution. The important subsystem in a configurable logic block is a Look-Up Table (LUT) in the FPGA chip. If the power reduction techniques are implemented in the LUTs, there would be an overall very less power while implementing the design in FPGAs. This study mainly focuses on designing LUTs using Programmable Read Only Memory (PROM) circuits. To implement these LUTs, half adder, full adder, half subtract and full subtractor circuits are chosen with PROM concept. Both the conventional CMOS and pseudo-nMOS style architectures are built for the LUTs. Pseudo-nMOS based LUTs are offering less area and low power compared with conventional CMOS approach. A pseudo-nMOS based full adder LUT design produce 564.5 μm 2 layout area, which is less compared with 765.5 μm 2 produced by conventional CMOS full adder LUT. A pseudo-nMOS based full subtractor design produce 1.119 μW dynamic power dissipation, which is less compared with 3.905 μW produced by conventional CMOS full subtractor. Also the design cycle time for FPGAs are much less compared with ASICs. Simulation results are verified using Microwind and Digital Schematic (DSCH) Electronic Computer Aided (CAD) design tools with BSIM4 MOSFET model in 60 nm technology. This study conveys that how the Programmable Read Only Memory (PROM) can act as a Look-Up Table (LUT) within a FPGA architecture. Since engineers are designing the circuits with most care with circuit design, layout design, etc., Application Specific Integrated Circuits (ASIC) are the best at providing low power, high speed and low size at the cost of design cycle time. But with the current semiconductor technology growth, even FPGAs are being manufactured with high speed with more versatile functionalities.

Towards modular design of reliable quantum-dot cellular automata logic circuit using multiplexers

With the rapid advancement in very large scale integration (VLSI) technology, it is the utmost necessity to achieve a reliable design with low power consumption. The Quantum dot Cellular Automata (QCA) can be such an architecture at nano-scale and thus emerges as a viable alternative for the current CMOS VLSI. This work targets design of logic module in QCA. It reports a modular design methodology to build the fault tolerant 2n:1 multiplexer with optimized wire-crossings, delay and power consumption. A 2:1 QCA multiplexer is proposed as the basic logic module that in turn is utilized to synthesize 4:1 and 8:1 multiplexers. It shows significant achievement in terms of clock speed (36%), wire-crossing (58%), fault tolerance (77.62%) and power consumption over the existing designs. The effectiveness of proposed multiplexer is further established through synthesis of configurable logic block (CLB) for field programmable gate arrays (FPGAs).

Hardware software partitioning of control data flow graph on system on programmable chip

A System On Programmable Chip (SOPC) is a circuit that integrates all components of an electronic system into a single chip. It may consist of memories, one or more microprocessors, interface devices, configurable logic blocks and other necessary components to achieve an intended function. In this paper, we propose a new hardware–software partitioning algorithm of control data flow graph for SOPC. The main aim of our algorithm is to find a best compromise between hardware and software implementation of operations in order to satisfy design constraints in terms of latency and hardware resources of the target application. Our algorithm has been evaluated on real hardware device. In fact, experimentations have been done using a real FPGA Virtex-5. Results have shown that our algorithm provides a better performing system with the lowest possible cost compared to existing approaches.

Stateful-NOR based reconfigurable architecture for logic implementation

Most commercial Field Programmable Gate Arrays (FPGAs) have limitations in terms of density, speed, configuration overhead and power consumption mostly due to the use of SRAM cells in Look-Up Tables (LUTs), configuration memory and programmable interconnects. Also, hardwired Application Specific Integrated Circuit (ASIC) blocks designed for high performance arithmetic circuits in FPGA reduce the area available for reconfiguration. In this paper, we propose a novel generalized hybrid CMOS-memristor based architecture using stateful-NOR gates as basic building blocks for implementation of logic functions. These logic functions are implemented on memristor nanocrossbar layers, while the CMOS layer is used for selection and connection of memristors. The proposed pipelined architecture combines the features of ASIC, FPGA and microprocessor based designs. It has high density due to the use of nanocrossbar layer and high throughput especially for arithmetic circuits. The proposed architecture for three input one output logic block is compared with conventional LUT based Configurable Logic Block (CLB) having the same number of inputs and outputs; which shows 1.82×area saving, 1.57×speedup and 3.63×less power consumption. The automation algorithm to implement any logic function using proposed architecture is also presented.

A Multi-Granularity FPGA With Hierarchical Interconnects for Efficient and Flexible Mobile Computing

Following the rapid expansion of mobile computing in the past decade, mobile system-on-a-chip (SoC) designs have off-loaded most compute-intensive tasks to dedicated accelerators to improve energy efficiency. An increasing number of accelerators in power-limited SoCs results in large regions of “dark silicon.” Such accelerators lack flexibility, thus any design change requires a SoC re-spin, significantly impacting cost and timeline. To address the need for efficiency and flexibility, this work presents a multi-granularity FPGA suitable for mobile computing. Occupying 20.5mm2 in 40nm CMOS, the chip incorporates 2,760 fine-grained configurable logic blocks (CLBs) with 11,040 6-input look-up-tables (LUTs) for random logic, basic arithmetic, shift registers, and distributed memories, 42 medium-grained 48b DSP processors for MAC and SIMD operations, 16 32K×1b to 512×72b reconfigurable block RAMs, and 2 coarsegrained kernels: a 64-8192-point fast Fourier transform (FFT) processor and a 16-core universal DSP (UDSP) for software-defined radio (SDR). Using a mixradix hierarchical interconnect, the chip achieves a 4× interconnect area reduction over commercial FPGAs for comparable connectivity, reducing overall area and leakage by 2.5×, and delivering a 10-50% lower active power. With coarse-grained kernels, the chip's energy efficiency reaches within 4-5× of ASIC designs.

Efficient Hardware Implementation of the Pipelined DES Encryption Algorithm Using FPGA

This paper presents a high throughput reconfigurable hardware implementation of DES Encryption algorithm.This achieved by using a new proposed implementation of the DES algorithm using superpipelinedconcept.DES are simulated using Xilinx 9.2i software with the use of VHDL as the hardware description languageand implemented using Spartan-3E FPGA kit.The DES Encryption algorithm achieved a high throughput of18.327Gbps and 3235 number of Configurable Logic Blocks (CLBs), obtaining the fastest hardware implementation with better area utilization.Comparison is made between the proposed implementation and other recent implementations. The comparison results indicate that a high throughput with optimized resource utilization scan be achieved using a super pipelined concept on the proposed design in a single FPGA chip.

Circuit Level Modeling of Extra Combinational Delays in SRAM-Based FPGAs Due to Transient Ionizing Radiation

This paper presents circuit level models that explain the extra combinational delays in a SRAM-based FPGA (Virtex-5) due to Single Event Upsets (SEUs). Several scenarios of extra combinational delays are simulated based on the circuit architecture of the FPGA core, namely Configurable Logic Blocks (CLBs) and routing. It is found that the main delay contribution originates from extra interconnection lines that are unintentionally connected to the main circuit path via pass transistors activated by SEUs. Moreover, longer delay faults observed on Input/Ouput Blocks (IOBs) due to SEU were investigated through simulations. In all cases, results are in close agreement with the ones obtained experimentally while exposing the FPGA to proton irradiation.

Providing Reliability of Physical Systems: Partially Programmable Circuit Design

One of the important properties of physical systems is reliability.of their functioning, in particular, reliability of functioning of logical control components of the systems. A new approach to partially programmable circuit design that allows masking stuck-at faults at gate poles of logical circuits is considered. The logical circuit consists of gates. It is supposed that only one gate pole may be fault. There are reserved programmable blocks configurable logic blocks (CLBs) based on Look Up Table (LUT) technology that may mask the fault. First, the suggested approach in contrast to the well-known ones, allows masking any stuck-at fault rather than a part of them. Second, the approach is oriented to deriving more simple masking circuit from CLBs based on a compact description of incompletely specified functions of subcircuits.