Efficient Hardware Implementation of the Pipelined DES Encryption Algorithm Using FPGA

Noor Najeeb Qaqos

doi:10.33899/rengj.2014.101018

Abstract

This paper presents a high throughput reconfigurable hardware implementation of DES Encryption algorithm.This achieved by using a new proposed implementation of the DES algorithm using superpipelinedconcept.DES are simulated using Xilinx 9.2i software with the use of VHDL as the hardware description languageand implemented using Spartan-3E FPGA kit.The DES Encryption algorithm achieved a high throughput of18.327Gbps and 3235 number of Configurable Logic Blocks (CLBs), obtaining the fastest hardware implementation with better area utilization.Comparison is made between the proposed implementation and other recent implementations. The comparison results indicate that a high throughput with optimized resource utilization scan be achieved using a super pipelined concept on the proposed design in a single FPGA chip.

Highlights

Data Encryption Standard (DES) is the most well-known cryptographic mechanism in history [1]
Manikonda [14].The Data Encryption Standard (DES) is a block cipher which means that during the encryption process, the plain-text is broken into fixed length blocks in 64 bits and each block is encrypted at the same time by using 56 bits key
This paper proposed a new hardware implementation of 16 rounds DES algorithm based on superpipelining concept

Summary

1- Introduction

Data Encryption Standard (DES) is the most well-known cryptographic mechanism in history [1]. V. Patel [9] presented a high performance reconfigurable hardware implementation of the DES algorithm achieved by combining pipelining concept with novel skew core key scheduling method. A DES algorithm implemented on FPGA using pipelined concept based on variable time data permutation described by K. FPGA implementation of DES algorithm based on real time data security applications presented by S. Each stage is divides into many stages and super pipelined resulting in 119 stage DES algorithm It allows 119 data blocks to be processed simultaneously resulting in an impressive gain in speed. After 16 rounds, the output is sent to final permutation which is an inverse to initial permutation to produce 64 bits cipher text [17]

2-1 Key Generation

5- Implementation Summary and Results

6- Conclusions