A Hybrid Logic Block Architecture in FPGA for Holistic Efficiency

Abstract

This brief presents a hybrid design of a configurable logic block (CLB) composed of look-up tables (LUTs) and universal logic gates (ULGs). A ULG is designed to realize holistic efficiency compared with the corresponding LUT. Previous designs with ULGs are either based on pure ULG or LUT-ULG complementary architecture, which incur a longer delay or double the area compared to the LUT-based design. In contrast, we propose a hybrid CLB that contains a mixture of LUTs and ULGs to address the generality problem as well as to achieve the holistic benefits including the area, performance, and power. To exploit the advantage of ULGs thoroughly while not causing negative side effects, the ratio of LUTs and ULGs in one CLB is explored by experiments. Experimental results show that, compared to pure LUT design, our proposed architecture design can save up to 17.1% logic power as well as 11.2% delay improvement and 10.4% logic area reduction. Compared to the state-of-the-art design, our proposed design has 3.8% improvement in power delay product and 17.1% improvement in area cost.